Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTS: |
JESD73 | Jun 1999 |
This standard covers specifications for a family of 5 V NMOS FET bus switch devices with 5 V TTL compatible control inputs. Not included in this document are device-specific parameters and performance levels that the vendor must also apply for full device description. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES: |
JESD80 | Nov 1999 |
The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS: |
JESD64-A | Oct 2000 |
The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V. Committee(s): JC-40 Free download. Registration or login required. |
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DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES: |
JESD76 | Apr 2000 |
This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established in JESD80. In this standard, the input and output conditions are described for CMOS Logic products in a 1.8 V (Normal Range) application. Committee(s): JC-40.1 Free download. Registration or login required. |
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DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS: |
JESD82 | Jul 2000 |
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES: |
JESD7-A | Aug 1986 |
This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION): |
JESD76-2 | Jun 2001 |
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION): |
JESD76-1 | Jun 2001 |
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS: |
JESD75-2 | Jul 2001 |
This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS: |
JESD75-3 | Jul 2001 |
This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |