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Title	Document #	Date
UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS	JESD8-23	Oct 2009
This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power supply voltage range in order to achieve lower power dissipation or higher performance. Committee(s): JC-16 Free download. Registration or login required.
STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18):	JESD8-15A	Sep 2003
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. Committee(s): JC-16 Free download. Registration or login required.
SERIAL INTERFACE FOR DATA CONVERTERS	JESD204C.01	Jan 2022
This is a minor editorial change to JESD204C, the details can be found in Annex A. This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this document. Informative sections are included to clarify and exemplify the standard. Item 192.02B. Committee(s): JC-16 Free download. Registration or login required.
SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400):	JESD8-13	Oct 2001
This standard defines the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nominally between 0 and 400 mV. Power supplies other than the nominal 800 mV power for the SLVS interface are not specified. Committee(s): JC-16 Free download. Registration or login required.
PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA):	JEP147	Oct 2003
This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. Committee(s): JC-16, JC-16.2 Free download. Registration or login required.
POD18 - 1.8 V PSEUDO OPEN DRAIN I/O	JESD8-19	Dec 2006
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A.01	Aug 2022
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21C.01	Jun 2022
Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required.
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O	JESD8-30A.01	Jun 2022
Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE	JESD8-24	Aug 2011
This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Committee(s): JC-16 Free download. Registration or login required.
POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE	JESD8-25	Sep 2011
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required.
PART MODEL SCHEMAS	JEP30-10v3-0-0	Aug 2023
This download includes all files under the parent schema JEP30-10v3-0-0 (Committees: JC-11, JC-11.2) including: JEP30-A101v2-0-1 (Assembly Process), Committees: JC-11, JC-11.2, JC-14 JEP30-E101v2-0-1 (Electrical), Committees: JC-11, JC-11.2, JC-16 JEP30-P101v3-0-0 (Package), Committees: JC-11, JC-11.2 JEP30-S101v1-0-1 (Supply Chain), Committees: JC-11, JC-11.2, JC-14 JEP30-T101v2-0-1 (Thermal) Committees: JC-11, JC-11.2, JC-15 JEP30-D10v3-0-0 (Types Dictionary) Committees: JC-11, JC-11.2 This will enable the user to validate the schemas. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16 Free download. Registration or login required.
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements	JEP30-E100B	Aug 2023
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-16 Free download. Registration or login required.
MULTI-WIRE MULTI-LEVEL I/O STANDARD	JESD247	Jun 2016
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00 Patents(): Kandou Committee(s): JC-16 Free download. Registration or login required.
INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS:	JESD8C.01	Sep 2007
This standard (a replacement of JEDEC Standards No. 8, 8-1, 8-1-A, and 8-A) defines dc interface parameters for a family of digital circuits operating from a power supply of nominal 3.0 V/3.3. V and driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for LVTTL-compatible and LVCMOS-compatible circuits. Committee(s): JC-16 Free download. Registration or login required.
INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS Status: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999.	JESD8-1A	Jun 1994
Committee(s): JC-16 Free download. Registration or login required.
I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD:	JESD67	Feb 1999
This standard attempts to aid in the design of electronic systems comprised of components that operate at several different supply voltages. This document covers respectively configurable I/O voltage, receiver type and switchpoint, and driver impedance. Committee(s): JC-16 Free download. Registration or login required.
HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT	JESD8-22B	Apr 2014
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. Committee(s): JC-16 Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS	JESD8-17	Nov 2004
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Committee(s): JC-16.1, JC-16 Free download. Registration or login required.

Standards & Documents Search

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS

STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18):

SERIAL INTERFACE FOR DATA CONVERTERS

SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400):

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA):

POD18 - 1.8 V PSEUDO OPEN DRAIN I/O

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE

PART MODEL SCHEMAS

Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

MULTI-WIRE MULTI-LEVEL I/O STANDARD

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS:

INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD:

HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS

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