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Displaying 36 - 39 of 39 documents. Show 5 | 10 | 20 results per page.

Title	Document #	Date
SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400):	JESD8-13	Oct 2001
This standard defines the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nominally between 0 and 400 mV. Power supplies other than the nominal 800 mV power for the SLVS interface are not specified. Committee(s): JC-16 Free download. Registration or login required.
Serial Interface for Data Converters	JESD204D	Dec 2023
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document. Committee(s): JC-16 Free download. Registration or login required.
STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18):	JESD8-15A	Sep 2003
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. Committee(s): JC-16 Free download. Registration or login required.
UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS	JESD8-23	Oct 2009
This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power supply voltage range in order to achieve lower power dissipation or higher performance. Committee(s): JC-16 Free download. Registration or login required.

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