Standards & Documents Search

Displaying 6 - 10 of 39 documents. Show 5 | 10 | 20 results per page.

Title	Document #	Date
1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-26	Sep 2011
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required.
1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-31	Mar 2018
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V. Committee(s): JC-16 Free download. Registration or login required.
300 mV INTERFACE	JESD8-28	Jun 2015
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. Committee(s): JC-16 Free download. Registration or login required.
ADDENDUM No. 1 to JESD8: INTERFACE STANDARD FOR LOW VOLTAGE TTL-COMPATIBLE (LVTTL) VLSI DIGITAL CIRCUITS Status: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999.	JESD8-1	Jun 1994
Committee(s): JC-16 Free download. Registration or login required.
ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS:	JESD8-11A.01	Sep 2007
This new standard provides specifications that will be used by several companies in new 1.5 V products designed in 0.12-0.15 um CMOS technologies, and in components that interface with them. The specifications allow limited interoperability with products using the existing JEDEC HSTL specification (JESD8-6). This version is a minor editorial revision as noted in Annex A. Committee(s): JC-16 Free download. Registration or login required.

Pages