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Displaying 11 - 15 of 39 documents. Show 5 | 10 | 20 results per page.

Title	Document #	Date
POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE	JESD8-25	Sep 2011
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required.
PART MODEL SCHEMAS	JEP30-10v7-0-0	Nov 2024
This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including: JEP30-A101v2-0-3 (Assembly Process), Committees: JC-11, JC-11.2, JC-14 JEP30-E101v4-1-0 (Electrical), Committees: JC-11, JC-11.2, JC-16 JEP30-P101v7-0-0 (Package), Committees: JC-11, JC-11.2 JEP30-S101v1-1-0 (Supply Chain), Committees: JC-11, JC-11.2, JC-14 JEP30-T101v2-0-3 (Thermal) Committees: JC-11, JC-11.2, JC-15 JEP30-D10v4-0-0 (Types Dictionary) Committees: JC-11, JC-11.2 This will enable the user to validate the schemas. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16 Free download. Registration or login required.
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements	JEP30-E100F	Nov 2024
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-16 Free download. Registration or login required.
MULTI-WIRE MULTI-LEVEL I/O STANDARD	JESD247	Jun 2016
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00 Patents(): Kandou Committee(s): JC-16 Free download. Registration or login required.
INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS:	JESD8C.01	Sep 2007
This standard (a replacement of JEDEC Standards No. 8, 8-1, 8-1-A, and 8-A) defines dc interface parameters for a family of digital circuits operating from a power supply of nominal 3.0 V/3.3. V and driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for LVTTL-compatible and LVCMOS-compatible circuits. Committee(s): JC-16 Free download. Registration or login required.

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