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Title	Document #	Date
PART MODEL SCHEMAS	JEP30-10v7-0-0	Nov 2024
This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including: JEP30-A101v2-0-3 (Assembly Process), Committees: JC-11, JC-11.2, JC-14 JEP30-E101v4-1-0 (Electrical), Committees: JC-11, JC-11.2, JC-16 JEP30-P101v7-0-0 (Package), Committees: JC-11, JC-11.2 JEP30-S101v1-1-0 (Supply Chain), Committees: JC-11, JC-11.2, JC-14 JEP30-T101v2-0-3 (Thermal) Committees: JC-11, JC-11.2, JC-15 JEP30-D10v4-0-0 (Types Dictionary) Committees: JC-11, JC-11.2 This will enable the user to validate the schemas. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16 Free download. Registration or login required.
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements	JEP30-E100F	Nov 2024
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-16 Free download. Registration or login required.
Serial Interface for Data Converters	JESD204D	Dec 2023
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document. Committee(s): JC-16 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A.01	Aug 2022
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21C.01	Jun 2022
Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required.
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O	JESD8-30A.01	Jun 2022
Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
1.05 V CMOS	JESD8-34	Apr 2020
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01 Committee(s): JC-16 Free download. Registration or login required.
0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)	JESD8-33	Jun 2019
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03 Committee(s): JC-16 Free download. Registration or login required.
1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-31	Mar 2018
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V. Committee(s): JC-16 Free download. Registration or login required.
0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)	JESD8-29	Dec 2016
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24. Committee(s): JC-16 Free download. Registration or login required.
MULTI-WIRE MULTI-LEVEL I/O STANDARD	JESD247	Jun 2016
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00 Patents(): Kandou Committee(s): JC-16 Free download. Registration or login required.
300 mV INTERFACE	JESD8-28	Jun 2015
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. Committee(s): JC-16 Free download. Registration or login required.
HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT	JESD8-22B	Apr 2014
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. Committee(s): JC-16 Free download. Registration or login required.
POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE	JESD8-25	Sep 2011
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required.
1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-26	Sep 2011
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE	JESD8-24	Aug 2011
This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Committee(s): JC-16 Free download. Registration or login required.
UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS	JESD8-23	Oct 2009
This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power supply voltage range in order to achieve lower power dissipation or higher performance. Committee(s): JC-16 Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS:	JESD8-14A.01	Sep 2007
This new standard provides specifications that will be used by several companies in new 1.0 V products designed in 0.10-0.12 um CMOS technologies, and in components that interface with them. This standard defines power supply voltage ranges, dc interface and switching parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compatible circuits. This version is a minor editorial revision as noted in Annex A. Committee(s): JC-16 Free download. Registration or login required.
1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS:	JESD8-12A.01	Sep 2007
This standard defines power supply voltage ranges, dc interface and switching parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compatible circuits. Committee(s): JC-16 Free download. Registration or login required.

Standards & Documents Search

PART MODEL SCHEMAS

Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

Serial Interface for Data Converters

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

1.05 V CMOS

0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)

1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)

MULTI-WIRE MULTI-LEVEL I/O STANDARD

300 mV INTERFACE

HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT

POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE

1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS:

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS:

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