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Title Document # Date

INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

Status: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999. 		JESD8-1A Jun 1994

Committee(s): JC-16

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BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V

 JESD8-16A Nov 2004

This standard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel buses, and a differential signaling interface suitable for clock applications or parallel differential buses. JEDEC BIC Standard JESD8-16A continues the tradition of the JESD8-xx standards, defining electrical interfaces for the industry as new technologies and bus requirements develop. Previously, JEDEC defined standard JESD8-6, the HSTL standard, for use in 1.5V electrical environments. BIC is similar to HSTL, except the power supply voltage has dropped from 1.5V to 1.2V, and interface requirements are tightened to allow much higher speeds

Committee(s): JC-16

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POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

 JESD8-24 Aug 2011

This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.
Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices.

Committee(s): JC-16

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POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE

 JESD8-25 Sep 2011

This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.

Committee(s): JC-16

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Serial Interface for Data Converters

 JESD204D Dec 2023

This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document.

Committee(s): JC-16

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ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

 JESD8-8 Aug 1996

This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.

Committee(s): JC-16

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POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

JESD8-21C.01 Jun 2022

Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B

Committee(s): JC-16

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HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT

 JESD8-22B Apr 2014

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.

Committee(s): JC-16

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ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT

 JESD8-5A.01 Sep 2007

This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for CMOS-compatible circuits.

Committee(s): JC-16

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1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

 JESD8-26 Sep 2011

This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices.

Committee(s): JC-16

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300 mV INTERFACE

 JESD8-28 Jun 2015

This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal
levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm.

Committee(s): JC-16

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MULTI-WIRE MULTI-LEVEL I/O STANDARD

 JESD247 Jun 2016

This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00

Patents(): Kandou

Committee(s): JC-16

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0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)

 JESD8-29 Dec 2016

This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24.

Committee(s): JC-16

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POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

 JESD8-30A.01 Jun 2022

Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo  Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices.

Committee(s): JC-16

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1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

 JESD8-31 Mar 2018

This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V.

Committee(s): JC-16

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0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)

 JESD8-33 Jun 2019

This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03

Committee(s): JC-16

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1.05 V CMOS

 JESD8-34 Apr 2020

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01

Committee(s): JC-16

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Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

 JEP30-E100G Feb 2025

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-16

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PART MODEL SCHEMAS

 JEP30-10v8-0-0 Feb 2025

This download includes all files under the parent schema JEP30-10v8-0-0 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-4 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v5-0-0 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v8-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-1-1 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-4 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-K101v1-0-0 (Design Rule Kits)
     
  • JEP30-M101v1-0-0 (ECAD Models Guidelines)
     
  • JEP30-D10v5-0-0 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16

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