Standards & Documents Search

Displaying 1 - 20 of 162 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Joint ESDA/JEDEC - CDM Technical User Guide	JTR002-01-22	Jan 2023
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jan 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IC LATCH-UP TEST	JESD78F.01	Dec 2022
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)	J-STD-020F	Dec 2022
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices	J-STD-035A	Dec 2022
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS	JESD47L	Dec 2022
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Committee(s): JC-14, JC-14.3 Available for purchase: $87.38 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
TEMPERATURE, BIAS, AND OPERATING LIFE	JESD22-A108G	Nov 2022
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Wire Bond Pull Test Methods	JESD22-B120	Nov 2022
This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES	JESD217A.01	Nov 2022
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required.
Customer Notification for Environmental Compliance Declaration Deviations	JESD262	Nov 2022
This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. Committee(s): JC-14.4 Free download. Registration or login required.
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES	JESD625C	Oct 2022
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Committee(s): JC-13, JC-14.1 Free download. Registration or login required.
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)	JEP164	Oct 2022
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required.
TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES	JESD22-B130	Sep 2022
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
EXTERNAL VISUAL	JESD22-B101D	Apr 2022
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required.
METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC DEVICE FAILURE MECHANISMS	JESD91B	Mar 2022
The method described in this document applies to all reliability mechanisms associated with electronic devices. The purpose of this standard is to provide a reference for developing acceleration models for defect-related and wear-out mechanisms in electronic devices. Committee(s): JC-14.3 Free download. Registration or login required.
TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES	JESD22-A120C	Jan 2022
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required.

Standards & Documents Search

Joint ESDA/JEDEC - CDM Technical User Guide

Survey On Latch-Up Testing Practices and Recommendations for Improvements

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

THERMAL SHOCK

IC LATCH-UP TEST

JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

TEMPERATURE, BIAS, AND OPERATING LIFE

Wire Bond Pull Test Methods

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

Customer Notification for Environmental Compliance Declaration Deviations

REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES

SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)

TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES

LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES

RECOMMENDED ESD-CDM TARGET LEVELS

EXTERNAL VISUAL

METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC DEVICE FAILURE MECHANISMS

TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: