Global Standards for the Microelectronics Industry
Standards & Documents Search
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PART MODEL SCHEMAS |
JEP30-10v7-0-0 | Nov 2024 |
This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including:
This will enable the user to validate the schemas. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16 Free download. Registration or login required. |
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Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements |
JEP30-S100A.01 | Nov 2024 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14.4 Free download. Registration or login required. |
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JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL |
JS-001-2024 | Oct 2024 |
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Free download. Registration or login required. |
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Wire Bond Pull Test Methods |
JESD22-B120.01 | Sep 2024 |
This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. Free download. Registration or login required. |
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Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites) |
JEP001-3B | Sep 2024 |
The publication provides methodologies for measurements to qualify a new semiconductor wafer process. Free download. Registration or login required. |
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Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements |
JEP30-A100B | Aug 2024 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14.4 Free download. Registration or login required. |
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Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA) |
JEP170A | Jun 2024 |
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Free download. Registration or login required. |
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Information Requirements for the Qualification of Solid State Devices |
JESD69D | Jun 2024 |
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Free download. Registration or login required. |
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Board Level Drop Test Method of Components for Handheld Electronic Products |
JESD22-B111A.01 | Jun 2024 |
This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components. Free download. Registration or login required. |
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Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly |
J-STD-609C.01 | Apr 2024 |
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd level terminal finish or material. Free download. Registration or login required. |
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Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors |
JEP199 | Apr 2024 |
This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors. Free download. Registration or login required. |
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Gate Dielectric Breakdown |
JESD263 | Mar 2024 |
This document describes procedures developed for estimating the overall integrity of gate dielectrics. JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92. Free download. Registration or login required. |
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Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress |
JEP154A | Mar 2024 |
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. Free download. Registration or login required. |
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Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices |
JESD625C.01 | Mar 2024 |
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Free download. Registration or login required. |
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Definition of “Low-Halogen” For Electronic Products |
JS709D | Jan 2024 |
This standard provides terms and definitions for “low-halogen” electronic products. Free download. Registration or login required. |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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Power Cycling |
JESD22-A122B | Nov 2023 |
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Free download. Registration or login required. |
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Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature |
JESD22-B112C | Nov 2023 |
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation. Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F.02 | Nov 2023 |
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Free download. Registration or login required. |
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Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications |
JESD22-B121 | Nov 2023 |
This test method covers X-ray imaging for terrestrial applications on packaged devices. Free download. Registration or login required. |
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A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces |
JEP196 | Nov 2023 |
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Free download. Registration or login required. |
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ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2022 | Jun 2023 |
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Free download. Registration or login required. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. Committee(s): JC-14 Free download. Registration or login required. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download. Registration or login required. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required. |
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STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed 4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed 04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required. |
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Temperature Cycling |
JESD22-A104F.01 | Apr 2023 |
This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing. Committee(s): JC-14.1 Free download. Registration or login required. |
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Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel) |
JEP130C | Feb 2023 |
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Free download. Registration or login required. |
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Joint ESDA/JEDEC - CDM Technical User Guide |
JTR002-01-22 | Jan 2023 |
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Free download. Registration or login required. |
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Survey On Latch-Up Testing Practices and Recommendations for Improvements |
JEP193 | Jan 2023 |
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Free download. Registration or login required. |
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THERMAL SHOCK |
JESD22-A106B.02 | Jan 2023 |
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Free download. Registration or login required. |
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JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs) |
J-STD-020F | Dec 2022 |
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Free download. Registration or login required. |
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JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices |
J-STD-035A | Dec 2022 |
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Free download. Registration or login required. |
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS |
JESD47L | Dec 2022 |
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Available for purchase: $87.38 Add to Cart Paying JEDEC Members may login for free access. |
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TEMPERATURE, BIAS, AND OPERATING LIFE |
JESD22-A108G | Nov 2022 |
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Free download. Registration or login required. |
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TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES |
JESD217A.01 | Nov 2022 |
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required. |
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Customer Notification for Environmental Compliance Declaration Deviations |
JESD262 | Nov 2022 |
This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. Committee(s): JC-14.4 Free download. Registration or login required. |
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SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED) |
JEP164 | Oct 2022 |
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required. |
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TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES |
JESD22-B130 | Sep 2022 |
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required. |
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LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES |
JEP160A | Aug 2022 |
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Free download. Registration or login required. |
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EXTERNAL VISUAL |
JESD22-B101D | Apr 2022 |
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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RECOMMENDED ESD-CDM TARGET LEVELS |
JEP157A | Apr 2022 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Free download. Registration or login required. |
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METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC DEVICE FAILURE MECHANISMS |
JESD91B | Mar 2022 |
The method described in this document applies to all reliability mechanisms associated with electronic devices. The purpose of this standard is to provide a reference for developing acceleration models for defect-related and wear-out mechanisms in electronic devices. Committee(s): JC-14.3 Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION |
JESD22-B118A | Nov 2021 |
This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE |
JESD89-3B | Sep 2021 |
This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER. Committee(s): JC-14.1 Free download. Registration or login required. |
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GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES |
JESD31F | Aug 2021 |
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE |
JESD89-2B | Jul 2021 |
This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source. Free download. Registration or login required. |
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TEST METHOD FOR REAL-TIME SOFT ERROR RATE |
JESD89-1B | Jul 2021 |
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Free download. Registration or login required. |
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METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITS |
JESD85A | Jul 2021 |
This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference to the way failure rates are calculated. Committee(s): JC-14.3 Free download. Registration or login required. |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |
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ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST |
JESD22-A118B.01 | May 2021 |
The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required. |
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HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST) |
JESD22-A110E.01 | May 2021 |
The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. This is a minor editorial edit to JESD22A110E, July 2015 approved by the formulating committee. Committee(s): JC-14.1 Free download. Registration or login required. |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS |
JEP178 | Apr 2021 |
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required. |
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FLIP CHIP TENSILE PULL |
JESD22-B109C | Mar 2021 |
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required. |
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APPLICATION THERMAL DERATING METHODOLOGIES: |
JEP149.01 | Jan 2021 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |