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Title	Document #	Date
Joint ESDA/JEDEC - CDM Technical User Guide	JTR002-01-22	Jan 2023
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jan 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IC LATCH-UP TEST	JESD78F.01	Dec 2022
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.

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