Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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WIRE BOND SHEAR TEST |
JESD22-B116B | May 2017 |
This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance. Free download. Registration or login required. |
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Wire Bond Pull Test Methods |
JESD22-B120.01 | Sep 2024 |
This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. Free download. Registration or login required. |
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VIBRATION, VARIABLE FREQUENCY |
JESD22-B103B.01 | Sep 2016 |
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). Committee(s): JC-14.1 Free download. Registration or login required. |
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USER GUIDE FOR MICROCIRCUIT FAILURE ANALYSIS:Status: RescindedNovember 2004 |
JEB16 | Jul 1970 |
This guide defines generalized procedures for the failure analysis of monolithic integrated microelectronic circuits. Although the generalized procedural steps may apply to all microelectronic circuits, additional analysis steps unique to thin/thick film hybrid devices are not covered. Committee(s): JC-14 Free download. Registration or login required. |
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UNDERSTANDING ELECTRICAL OVERSTRESS - EOSStatus: Reaffirmed May 2022 |
JEP174 | Sep 2016 |
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required. |
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TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION:Status: Rescinded |
JES2 | Jul 1992 |
Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft communications transmitters. Identifies the electrical parameters, wafer acceptance tests, screening tests, qualification tests, and lot acceptance tests pertinent to power GaAs FETs. Applicable to packaged and chip-carrier parts; portions may not be applicable to unpackaged and unmounted chips. **This document was rescinded on October 17, 2024, but is available for download for reference. purposes. Committee(s): JC-14.7 Free download. Registration or login required. |
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THERMAL SHOCK |
JESD22-A106B.02 | Jan 2023 |
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES |
JESD217A.01 | Nov 2022 |
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required. |
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Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications |
JESD22-B121 | Nov 2023 |
This test method covers X-ray imaging for terrestrial applications on packaged devices. Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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TEST METHOD FOR REAL-TIME SOFT ERROR RATE |
JESD89-1B | Jul 2021 |
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Free download. Registration or login required. |
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TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES |
JESD22-B130 | Sep 2022 |
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required. |
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TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE |
JESD89-3B | Sep 2021 |
This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER. Committee(s): JC-14.1 Free download. Registration or login required. |
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TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE |
JESD89-2B | Jul 2021 |
This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source. Free download. Registration or login required. |
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TEMPERATURE, BIAS, AND OPERATING LIFE |
JESD22-A108G | Nov 2022 |
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Free download. Registration or login required. |
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Temperature Cycling |
JESD22-A104F.01 | Apr 2023 |
This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing. Committee(s): JC-14.1 Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED) |
JEP164 | Oct 2022 |
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required. |
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SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHESStatus: ReaffirmedApril 2023 |
JEP161 | Jan 2011 |
This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases. Free download. Registration or login required. |
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SYMBOL AND LABELS FOR MOISTURE-SENSITIVE DEVICES - SUPERSEDED BY J-STD-033, April 2018.Status: Rescinded, November 2018 |
JEP113B | May 1999 |
Certain PSMC (Plastic Surface-mount Components) are subject to permanent damage due to moisture-induced failures encountered during high-temperature surface-mount processing unless appropriate precautions are observed. The purpose of this publication is to provide a distinctive symbol and labels to be used to identify those devices that require special packing and handling precautions. Committee(s): JC-14.1 Free download. Registration or login required. |
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SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICESStatus: Reaffirmed October 1988, September 1996, September 2009, May 2018, October 2024 |
JESD471 | Feb 1980 |
This standard will be useful to anyone engaged in handling semiconductor devices and integrated circuits that are subject to permanent damage due to electrostatic potentials. The standard establishes a symbol and label that will gain the attention of those persons who might inflict electrostatic damage to the device. The label which is placed on the lowest practical level of packaging contains the words 'ATTENTION - OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES'. The symbol contained in this label, which may be used on the device itself, shows a hand in a triangle with a bar through it. Formerly known as EIA-471. Free download. Registration or login required. |
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Survey On Latch-Up Testing Practices and Recommendations for Improvements |
JEP193 | Jan 2023 |
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Free download. Registration or login required. |
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SUPERSEDED BY THE TEST METHODS INDICATED BY 'JESD22-'Status: Superseded |
JESD22- B | Jan 2000 |
A complete set of test methods can be obtained from Global Engineering Documents Committee(s): JC-14.1 |
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS |
JESD47L | Dec 2022 |
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Available for purchase: $87.38 Add to Cart Paying JEDEC Members may login for free access. |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST |
JESD22-A101D.01 | Jan 2021 |
This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Free download. Registration or login required. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. Committee(s): JC-14 Free download. Registration or login required. |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed 04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required. |
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STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE:Status: Reaffirmed October 2012, September 2018 |
JESD33B | Feb 2004 |
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed 4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD: |
JESD37A | Aug 2017 |
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:Status: Rescinded January 2025 |
JESD38 | Dec 1995 |
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required. |
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SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENTStatus: Reaffirmed |
JESD50C | Jan 2018 |
This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability. Free download. Registration or login required. |
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SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES |
JEP143D | Jan 2019 |
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Free download. Registration or login required. |
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SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES:Removed 01/21/04 Release Number: B |
J-STD-002 | Feb 2003 |
At the request of IPC, J-STD-002B has been removed from the free download area. In its place, JEDEC's Test Method, JESD22-B102, Solderability, which includes lead-free, was made available until it was replaced by J-STD-002D.
Any revision to J-STD-002 will no longer be available for free to the industry on the JEDEC website. However, the document is available to the JEDEC formulating Committee members, in the Members Area.
If you are not a JEDEC member you may wish to try the IPC website or one of the resellers listed at: http://www.jedec.org/standards-document |
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SOLDERABILITYStatus: Rescinded 2014, this document has been replaced by J-STD-002D. |
JESD22-B102E | Oct 2007 |
This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment. Committee(s): JC-14.1 |
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SOLDER BALL SHEARStatus: Reaffirmed September 2020 |
JESD22-B117B | May 2014 |
The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball shear is a destructive test. Free download. Registration or login required. |
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SOLDER BALL PULLStatus: Reaffirmed September 2021 |
JESD22-B115A.01 | Jul 2016 |
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A. Free download. Registration or login required. |
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SIGNATURE ANALYSIS:Status: Reaffirmed January 2025 |
JEP136 | Jul 1999 |
Signature Analysis is a method to reduce the number of comprehensive physical failure analyses by the application of statistical inference techniques. The purpose of this document is to promote a common definition of Signature Analysis by inference, using the same statistical techniques, and to recognize that it is formal means of doing failure analysis.
Committee(s): JC-14.4 Free download. Registration or login required. |