Standards & Documents Search

This download includes all files under the parent schema JEP30-10v6-0-0 (Committees: JC-11, JC-11.2) including:

• JEP30-A101v2-0-3 (Assembly Process),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-E101v4-0-0 (Electrical),
  
  • Committees: JC-11, JC-11.2, JC-16
• JEP30-P101v6-0-0 (Package),
  
  • Committees: JC-11, JC-11.2
• JEP30-S101v1-0-3 (Supply Chain),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-T101v2-0-3 (Thermal)
  
  • Committees: JC-11, JC-11.2, JC-15
• JEP30-D10v4-0-1 (Types Dictionary)
  
  • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14.4

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This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices.

Committee(s): JC-14, JC-14.1

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This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

Committee(s): JC-14, JC-14.4

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This document describes procedures developed for estimating the overall integrity of gate dielectrics.

JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92.

Committee(s): JC-14, JC-14.2

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This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages.

Committee(s): JC-14, JC-14.1

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This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices.

Committee(s): JC-14, JC-14.3

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This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation.

Committee(s): JC-14, JC-14.1

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This test method covers X-ray imaging for terrestrial applications on packaged devices.

Committee(s): JC-14, JC-14.1

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This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits

Committee(s): JC-14, JC-14.1

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This standard specifies the general requirements of a statistical process control (SPC) system. 
This is a revision of JESD557C.

Committee(s): JC-14

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This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

Committee(s): JC-14.3

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This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

Committee(s): JC-14.2, JC-14.21

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This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality.

Committee(s): JC-14, JC-14.4

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This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry.

Committee(s): JC-14, JC-14.1

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The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations.

Committee(s): JC-14, JC-14.1

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This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

Committee(s): JC-14, JC-14.3

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This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures.

Committee(s): JC-14.1

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This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology.

Committee(s): JC-14.3

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