Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING |
JEP118A | Dec 2018 |
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required. |
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Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel) |
JEP130C | Feb 2023 |
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Free download. Registration or login required. |
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GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS:Status: Reaffirmed January 2025 |
JEP134 | Sep 1998 |
The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis. Committee(s): JC-14.4 Free download. Registration or login required. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download. Registration or login required. |
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GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETS: |
JEP110 | Jul 1988 |
This publication is intended for power GaAs FET applications requiring high reliability. An accurate measurement of thermal resistance is extremely important to provide the user with knowledge of the FETs operating temperature so that more accurate life estimates can be made. FET failure mechanisms and failure rates have, in general, an exponential dependence on temperature (which is why temperature-accelerated testing is successful). Because of the exponential relationship of failure rate with temperature, the thermal resistance should be referenced to the hottest part of the FET. Committee(s): JC-14.7 Free download. Registration or login required. |
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GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999.Status: RescindedNovember 1999 |
JEP124 | Dec 1995 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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GUIDELINES FOR USER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERS - SUPERSEDED BY JESD46, August 1997.Status: Rescinded |
JEP117 | Apr 1994 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA) |
JEP170A | Jun 2024 |
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Free download. Registration or login required. |
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HERMETICITYStatus: Reaffirmed September 2017 |
JESD22-A109B | Nov 2011 |
Testing for hermeticity on commercial product is not normally done on standard molded devices that are not hermetic. Commercial product that this test method applies to has a construction that produces a hermetic package; examples of this are ceramic and metal packages. Most of these tests are controlled and updated in the military standards, the two standards that apply are MIL-STD-750 for discretes, & MIL-STD-883 for microcircuits. The test within these standards can be used for all package types. Within these standards the tests are similar; MIL-STD-750 Test Method 1071 Hermetic Seal is recommended for any commercial hermetic requirements. For MIL-STD-883 the applicable test method is 1014 Seal. Committee(s): JC-14.1 Free download. Registration or login required. |
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HIGH TEMPERATURE CONTINUITYStatus: Rescinded November 1999 |
JESD22-C100-A | Jan 1990 |
Committee(s): JC-14.1 |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |
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HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST) |
JESD22-A110E.01 | May 2021 |
The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. This is a minor editorial edit to JESD22A110E, July 2015 approved by the formulating committee. Committee(s): JC-14.1 Free download. Registration or login required. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F.02 | Nov 2023 |
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Free download. Registration or login required. |
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Information Requirements for the Qualification of Solid State Devices |
JESD69D | Jun 2024 |
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Free download. Registration or login required. |
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IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702) |
JS9702 | Jun 2004 |
This publication specifies a common method of establishing the fracture resistance of board-level device interconnects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/fail requirements are typically specific to each device application and are outside the scope of this document. This version contains Addendum 1, May 2015, reposted 8/15/2016. Committee(s): JC-14.1 Free download. Registration or login required. |
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IPC/JEDEC-9703: MECHANICAL SHOCK TEST GUIDELINE FOR SOLDER JOINT RELIABILITYStatus: Reaffirmed May 2014, May 2019 |
JS9703 | Mar 2009 |
This document establishes mechanical shock test guidelines for assessing solder joint reliability of Printed Circuit Board (PCB) assemblies from system to component level. Committee(s): JC-14.1 Free download. Registration or login required. |
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IPC/JEDEC-9704A: PRINTED WIRING BOARD (PWB) STRAIN GAGE TEST GUIDELINE |
JS9704A | Jan 2012 |
This document describes specific guidelines for strain gage testing for Printed Wiring Board (PWB)assemblies. The suggested procedures enables board manufacturers to conduct required strain gage testing independently, and provides a quantitative method for measuring board flexure, and assessing risk levels. The topics covered include: Test setup and equipment; requirements; Strain measurement; Report format Free download. Registration or login required. |
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ISOTHERMAL ELECTROMIGRATION TEST PROCEDUREStatus: Reaffirmed April 2025 |
JESD61A.01 | Oct 2007 |
This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test. Free download. Registration or login required. |
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Joint ESDA/JEDEC - CDM Technical User Guide |
JTR002-01-22 | Jan 2023 |
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Free download. Registration or login required. |
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