Standards & Documents Search

Displaying 41 - 60 of 162 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jan 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES	JESD22-A111B	Mar 2018
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
EXTERNAL VISUAL	JESD22-B101D	Apr 2022
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING Status: Reaffirmed June 2011, May 2022	JESD659C	Apr 2017
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996. Status: Superseded	JESD29-A	Jul 1996
Committee(s): JC-14.3 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES Status: Rescinded, November 2004	JESD34	Mar 1993
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required.
FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS Status: Rescinded February 2020	JESD22-C101F	Oct 2013
The material in this test method has been superseded by JS-002-2018, published January 2019, which in turn has been superseded by JS-002-2022, published January 2023. Committee(s): JC-14, JC-14.1
FLIP CHIP TENSILE PULL	JESD22-B109C	Mar 2021
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)	JEP001-1A	Sep 2018
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)	JEP001-2A	Sep 2018
This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)	JEP001-3A	Sep 2018
This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES	JESD31F	Aug 2021
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Committee(s): JC-13, JC-14.4 Free download. Registration or login required.
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING: Status: Rescinded September 2021 (JC-14.2-21-182)	JEP128	Nov 1996
This guide has be replaced by JESD241, September 2021 Committee(s): JC-14.2
GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE	JEP70C	Oct 2013
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. Committee(s): JC-14.4 Free download. Registration or login required.
GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESS Status: ReaffirmedJune 2011	JEP154	Jan 2008
This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING: Status: ReaffirmedOctober 2012	JEP139	Dec 2000
This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking. Committee(s): JC-14.2 Free download. Registration or login required.
GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING	JEP118A	Dec 2018
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required.
GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING (Tubes, Trays, and Tape and Reel)	JEP130B	Nov 2016
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Committee(s): JC-14.4 Free download. Registration or login required.
GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS:	JEP134	Sep 1998
The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis. Committee(s): JC-14.6 Free download. Registration or login required.

Standards & Documents Search

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES

EXTERNAL VISUAL

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996.

FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES

FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS

FLIP CHIP TENSILE PULL

FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)

FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING:

GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE

GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESS

GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING:

GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING

GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING (Tubes, Trays, and Tape and Reel)

GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS:

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: