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Title	Document #	Date
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions	JEP158	Nov 2009
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces	JEP196	Nov 2023
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
A PROCEDURE FOR EXECUTING SWEAT: Status: Reaffirmed October 2012, September 2018	JEP119A	Aug 2003
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:	JESD28-A	Dec 2001
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS:	JESD60A	Sep 2004
This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES Status: Rescinded September 2021 (JC-14.2-21-183)	JESD90	Nov 2004
This document hasbeen replaced by JESD241, September 2021. Committee(s): JC-14, JC-14.2
ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE Status: Reaffirmed January 2021	JESD22-A102E	Jul 2015
This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test that employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST	JESD22-A118B.01	May 2021
The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES	JEP176	Jan 2018
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and reliability testing. These tests are used frequently in qualifying integrated circuits as a new product, a product family, or as products in a process which is being changed. Committee(s): JC-14.3 Free download. Registration or login required.
Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS	JESD28-1	Sep 2001
This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis techniques. Committee(s): JC-14.2 Free download. Registration or login required.
ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS Status: Rescinded	JESD35-1	Sep 1995
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2
ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35-2	Feb 1996
JESD35-2 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures. Committee(s): JC-14.2
APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY Status: Reaffirmed January 2021	JESD94B	Oct 2015
The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments. Committee(s): JC-14.3 Free download. Registration or login required.
APPLICATION THERMAL DERATING METHODOLOGIES:	JEP149.01	Jan 2021
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES Status: ReaffirmedJune 2006, September 2011, January 2015	JEP140	Jun 2002
The beaded thermocouple temperature measurement guideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications can include, but not limited to, temperature profile measurement in reliability test chambers and solder reflow operations that are associated with component assembly to printed wiring boards. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS	JESD22-B113B	Aug 2018
The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Board Level Drop Test Method of Components for Handheld Electronic Products	JESD22-B111A.01	Jun 2024
This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURES Status: Reaffirmed September 2019	JEP153A	Mar 2014
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES	JEP167A	Nov 2020
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required.
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION	JEP156A	Mar 2018
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.

Standards & Documents Search

3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces

A PROCEDURE FOR EXECUTING SWEAT:

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS:

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES

ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE

ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST

ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES

Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS

ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS

ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS:

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY

APPLICATION THERMAL DERATING METHODOLOGIES:

BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS

Board Level Drop Test Method of Components for Handheld Electronic Products

CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURES

CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

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