Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices |
J-STD-035A | Dec 2022 |
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Free download. Registration or login required. |
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JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES |
J-STD-033D | Apr 2018 |
The purpose of this document is to provide manufacturers and users with standardized methods for handling, packing, shipping, and use of moisture/reflow and process sensitive devices that have been classified to the levels defined in J-STD-020 or J-STD-075. These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and damage-free reflow can be achieved. The dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date. Free download. Registration or login required. |
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JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs) |
J-STD-020F | Dec 2022 |
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Free download. Registration or login required. |
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JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL |
JS-001-2024 | Oct 2024 |
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Free download. Registration or login required. |
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JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE |
J-STD-048 | Nov 2014 |
This document supersedes JESD48. This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. The goal of this notification standard is to better enable customers to manage and mitigate the disruption caused by the discontinuation of a product and ensure continuity of supply. This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition ongoing requirements to alternate products. Committee(s): JC-14.4 Free download. Registration or login required. |
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LEAD INTEGRITYStatus: Reaffirmed - May 2023 |
JESD22-B105E | Feb 2017 |
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. Free download. Registration or login required. |
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LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES |
JEP160A | Aug 2022 |
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Free download. Registration or login required. |
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LOW TEMPERATURE STORAGE LIFEStatus: Reaffirmed May 2021 |
JESD22-A119A | Oct 2015 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any). Committee(s): JC-14.1 Free download. Registration or login required. |
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MARK LEGIBILITY |
JESD22-B114B | Jan 2020 |
This standard describes a nondestructive test to assess solid state device mark legibility. The specification applies only to solid state devices that contain markings, regardless of the marking method. It does not define what devices must be marked or the method in which the device is marked, i.e., ink, laser, etc. The standard is limited in scope to the legibility requirements of solid state devices, and does not replace related reference documents listed in this standard. Committee(s): JC-14.1 Free download. Registration or login required. |
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MARKING PERMANENCYStatus: Reaffirmed August 2024 |
JESD22-B107D | Mar 2011 |
This test method provides two tests for determining the marking permanency of ink marked integrated circuits. A new non-destructive tape test method is introduced to quickly determine marking integrity. The test method also specifies a resistance to solvents method based upon MIL Std 883 Method 2015. Free download. Registration or login required. |
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