Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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CLASSIFICATION OF PASSIVE AND SOLID STATE DEVICES FOR ASSEMBLY PROCESSES |
J-STD-075A | May 2018 |
This is a Joint Standard between ECIA, IPC, and JEDEC. The purpose of this specification is to establish an agreed to set of worst case solder assembly process conditions to which devices are evaluated. The generated PSL rating will convey the conditions to which a device can be safely attached to FR4 type or ceramic laminates using SMT reflow and solder wave/fountain soldering processes. It is important for device manufacturers (hereafter referred to as “suppliers”), users, and (PWB) assemblers to be highly familiar with this standard’s information and processes to insure optimal device quality and reliability. THIS DOCUMENT IS NOT AVAILABLE FOR FREE DOWNLOAD. However, this document is available to the JEDEC formulating Committee members on the JC-14 Resources tab on the Members' website. The lead organization is ECIA. Committee(s): JC-14 |
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COMPONENT PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS - SUPERSEDED BY EIA-671, November 1996.Status: Superseded |
JESD43 | Nov 1996 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING |
JESD214.01 | Aug 2017 |
This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Committee(s): JC-14.2 Free download. Registration or login required. |
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COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICESStatus: Reaffirmed February 2023 |
JESD22-B108B | Sep 2010 |
The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used. Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINEStatus: Reaffirmed February 2023 |
JP002 | Mar 2006 |
This document will provide insight into the theory behind tin whisker formation as it is known today and, based on this knowledge, potential mitigation practices that may delay the onset of, or prevent tin whisker formation. The potential effectiveness of various mitigation practices will also be briefly discussed. References behind each of the theories and mitigation practices are provided. Free download. Registration or login required. |
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Customer Notification for Environmental Compliance Declaration Deviations |
JESD262 | Nov 2022 |
This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. Committee(s): JC-14.4 Free download. Registration or login required. |
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CUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SOLID-STATE SUPPLIERSStatus: SupersededBy J-STD-046, July 2016 |
JESD46D | Dec 2011 |
This standard establishes procedures to notify customers of semiconductor product and process changes. Requirements include: documentation; procedures for classification, notification and customer response; content; and records. Documentation of a suppliers change notification system should set clear and understandable expectations for both the originators of the change and their end customers. |
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CUSTOMER NOTIFICATION PROCESS FOR DISASTERS |
JESD246A | Jan 2020 |
This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within. Committee(s): JC-14.4 Free download. Registration or login required. |
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CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS |
J-STD-046 | Jul 2016 |
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required. |
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