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Title	Document #	Date
SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHES Status: ReaffirmedApril 2023	JEP161	Jan 2011
This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS	J-STD-046	Jul 2016
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required.
UNDERSTANDING ELECTRICAL OVERSTRESS - EOS Status: Reaffirmed May 2022	JEP174	Sep 2016
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required.
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS	JESD47L	Dec 2022
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Committee(s): JC-14, JC-14.3 Available for purchase: $87.38 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
VIBRATION, VARIABLE FREQUENCY	JESD22-B103B.01	Sep 2016
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). Committee(s): JC-14.1 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart Paying JEDEC Members may login for free access.
DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION Status: Reaffirmed September 2020	JEP172A	Jul 2015
Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry. Committee(s): JC-14.3 Free download. Registration or login required.
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM) This document is inactive as of September 2016	JESD22-A115C	Nov 2010
JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Qualification of Integrated Circuits). Machine Model (MM) as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only human-body model (HBM) and charged-device model (CDM) are the necessary ESD qualification test methods as specified in JESD47. Refer to JEP172: Discontinuing Use of the Machine Model for Device ESD Qualification for more information. Committee(s): JC-14.1
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL	JS-001-2024	Oct 2024
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jun 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.

Standards & Documents Search

SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHES

CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS

UNDERSTANDING ELECTRICAL OVERSTRESS - EOS

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

VIBRATION, VARIABLE FREQUENCY

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION

ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)

JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

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