Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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SIGNATURE ANALYSIS:Status: Reaffirmed January 2025 |
JEP136 | Jul 1999 |
Signature Analysis is a method to reduce the number of comprehensive physical failure analyses by the application of statistical inference techniques. The purpose of this document is to promote a common definition of Signature Analysis by inference, using the same statistical techniques, and to recognize that it is formal means of doing failure analysis.
Committee(s): JC-14.4 Free download. Registration or login required. |
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TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION:Status: Rescinded |
JES2 | Jul 1992 |
Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft communications transmitters. Identifies the electrical parameters, wafer acceptance tests, screening tests, qualification tests, and lot acceptance tests pertinent to power GaAs FETs. Applicable to packaged and chip-carrier parts; portions may not be applicable to unpackaged and unmounted chips. **This document was rescinded on October 17, 2024, but is available for download for reference. purposes. Committee(s): JC-14.7 Free download. Registration or login required. |
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MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.Status: Rescinded, May 2000 |
JESD22-A112-A | Nov 1995 |
J-STD-020 is now on revision F. Free download. Registration or login required. |
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RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICESStatus: Reaffirmed February 2023 |
JESD22-B106E | Nov 2016 |
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s): JC-14.1 Free download. Registration or login required. |
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A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS: |
JESD28-A | Dec 2001 |
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICESStatus: Rescinded, November 2004 |
JESD34 | Mar 1993 |
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required. |
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PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS:Status: Rescinded |
JESD35A | Apr 2001 |
JESD35A was rescinded by the committee in June 2024 and has been superseded by JESD263. The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown. Committee(s): JC-14.2 |
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ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSStatus: Rescinded |
JESD35-1 | Sep 1995 |
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2 |
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ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS:Status: Rescinded |
JESD35-2 | Feb 1996 |
JESD35-2 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures. Committee(s): JC-14.2 |
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STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:Status: Rescinded January 2025 |
JESD38 | Dec 1995 |
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required. |