Global Standards for the Microelectronics Industry
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Displaying 1 - 4 of 4 documents.
Title | Document # | Date |
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A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES |
JESD90 | Nov 2004 |
This document describes an accelerated stress and test methodology for measuring device paramete Free download. Registration or login required. |
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POWER AND TEMPERATURE CYCLING |
JESD22-A105D | Jan 2020 |
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. Free download. Registration or login required. |
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THERMAL SHOCK |
JESD22-A106B.01 | Nov 2016 |
This test is conducted to determine the resistance of a part to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14.1 Free download. Registration or login required. |
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TEMPERATURE, BIAS, AND OPERATING LIFE |
JESD22-A108F | Jul 2017 |
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Committee(s): JC-14.1 Available for purchase: $54.00 Add to Cart Paying JEDEC Members may login for free access. |