Global Standards for the Microelectronics Industry
JEDEC DDR5 Workshop: Event Details
|About the Workshop||
JEDEC’s DDR5 Workshop will offer an unparalleled opportunity to receive an in-depth technical review of the upcoming DDR5 standard, as taught by industry experts involved in its development. Attendees will gain an insight into DDR5’s wide range of innovative features and device operation, as well as current and planned technological enablements to facilitate adoption of DDR5. Registration includes one complimentary digital download of the JEDEC DDR5 standard when published. Publication is forecast for year-end 2019.
The DDR5 Workshop will include detailed technical content that builds on previous generation devices and assumes that attendees are well-versed in previous generation memory technologies and standards. All attendees of the DDR5 Workshop who do not already have an in-depth understanding of memory technology and/or memory interface design should also attend the preceding Memory Tutorial session in order to maximize their comprehension of the material presented during the two-day DDR5 Workshop.
California: Tuesday, October 8 & Wednesday, October 9
Taiwan: Tuesday, October 15 & Wednesday, October 16
Marriott Santa Clara
Parking: Discounted self-parking: $6 per day per car. Single entry (cannot leave and return).
The Ambassador Hotel Hsinchu
Register for California events: https://www.jedec.org/register-ca
Register for Taiwan events: https://www.jedec.org/register-taiwan
|Accommodations||JEDEC does not have a block of sleeping rooms for this event. For assistance in locating accommodations, please review hotel options provided by the Santa Clara Convention and Visitors Bureau.|
|Sponsorships||A limited number of sponsorships are available for the California events: https://www.jedec.org/sites/default/files/SponsorshipRev.pdf|
General questions: Angie Steigleman at firstname.lastname@example.org