DDR5 Workshop: Day 2 Agenda

What makes DDR5 so different from DDR4? Many of the new features will make DDR5 differentiated from its predecessor, but not as much as its performance-boost and power-savings. DDR5 will come with longer burst length and same bank refresh powered by lower VDD/VPP, and this combination produces substantial improvement such as 2X better effective bandwidth and lower power consumption. This session will identify features that DDR5 adopted to enable those two features to be evolved from DDR4.

With memory speeds increasing at a rapid rate, the technical team at JEDEC needed a new novel method to solve the IO challenges. This presentation will attempt to educate the audience of the challenges faced during the evolution of DDR5 IO. The presentation will delve into, first use of DFE in DRAM, RCD and DB. Also included input measurement levels, command address, CA bus voltage and timing parameters, clock jitter, clock voltage sensitivity, DQ and DQS jitter and DDQ/DQS voltage sensitivity, Tx and Rx stressed eye, DDR5 equalization, I/O test and measurement philosophy and equalization training. We will also cover statistical methods and analysis of the DDR5 I/O subsystem.

There’s the standard, and then there’s how to measure it. Usually the specification drives measurement procedures but at DDR5 speeds development must go hand-in-hand to ensure that what works in theory will not only work in practice, but can be confirmed on the lab bench and in production. This session focuses on the DDR5 measurement methodologies that have been driven by the specification and the practical considerations that have influenced the DDR5 specification. Probing and test fixturing, use of new DFT features in the DDR5 specification itself, measurement algorithms and automation, and specific examples are presented that enable characterization and troubleshooting of DDR5 memory and support devices, DIMMs, as well as entire systems, both server and embedded.

This presentation provides an overview for all support devices for DDR5 RDIMM/LRDIMM family. It will cover in depth tutorial of Power Management device (PMIC) operation of RDIMM /LRDIMM as well as review of DDR5 SPD Hub device, DDR5 Register (RCD), DDR5 Data Buffer (DB) and DDR5 Thermal Sensor (TS) device for DDR5 RDIMM/LRDIMM family. The presentation will provide the detail tutorial of management bus interface using the I3C basic interface standard for DDR5 DIMM family of products.