JEDEC DDR5 Workshop: Day 2 Agenda

Wednesday, October 9 • Santa Clara, CA


Wednesday, October 16 • Hsinchu, Taiwan

8:30-9:00AMOnsite check-in for registered attendees
9:00-10:30AM
 

DDR5 Signaling and Timing Design & Analysis

Presenter: Arvind Kumar, Intel

With memory speeds increasing at a rapid rate, the technical team at JEDEC needed a new novel method to solve the IO challenges. This presentation will attempt to educate the audience of the challenges faced during the evolution of DDR5 IO. The presentation will delve into, first use of DFE in DRAM, RCD and DB. Also included input measurement levels, command address, CA bus voltage and timing parameters, clock jitter, clock voltage sensitivity, DQ and DQS jitter and DDQ/DQS voltage sensitivity, Tx and Rx stressed eye, DDR5 equalization, I/O test and measurement philosophy and equalization training. We will also cover statistical methods and analysis of the DDR5 I/O subsystem.

10:30-10:45AM Break

10:45-11:45AM
 

Interface Test and Validation Methodology

Presenter: Perry Keller, Keysight

There’s the standard, and then there’s how to measure it. Usually the specification drives measurement procedures but at DDR5 speeds development must go hand-in-hand to ensure that what works in theory will not only work in practice, but can be confirmed on the lab bench and in production. This session focuses on the DDR5 measurement methodologies that have been driven by the specification and the practical considerations that have influenced the DDR5 specification. Probing and test fixturing, use of new DFT features in the DDR5 specification itself, measurement algorithms and automation, and specific examples are presented that enable characterization and troubleshooting of DDR5 memory and support devices, DIMMs, as well as entire systems, both server and embedded.

11:45AM-Noon
 

DDR5 In-System Test Features and Challenges

Presenter: Barb Aichinger, FuturePlus

The system has booted and you suspect you have a problem on the DDR5 memory bus. How will you solve it? DDR5 offers challenges not seen before in DDR4. The standard tools used for DDR4 will not be available for DDR5. This presentation will take a quick look at the problems and the evolutionary path the industry is taking to solve these in system test and validation challenges.

Noon-1:00PMLunch
1:00-1:45PM
 

DDR5 Module Overview & JEDEC Release Plans

Presenter: Desi Rhoden, Montage

DDR5 Modules, also known as DDR5 DIMMs are the primary user accessible components for DDR5 memory and incorporate a host of new and improved architectures and logic devices compared to DDR4 modules. The presentation will provide an overview of the new DDR5 DIMM module families, potential applications for each DIMM type, on-DIMM voltage regulation, signal buffering, DIMM sideband bus connectivity, temperature sensing, DIMM pinouts, and current DIMM reference design plans. The presentation will include references to the memory and various logic devices as they are used on these DIMMs and comparisons to previous generation DDR4 DIMMs. Specific design and function details of the individual logic devices are covered in another presentation.

1:45-3:15PM

DDR5 Module Support Outlook

Presenter: Sam Patel, IDT

This presentation provides an overview for all support devices for DDR5 RDIMM/LRDIMM family. It will cover in depth tutorial of Power Management device (PMIC) operation of RDIMM /LRDIMM as well as review of DDR5 SPD Hub device, DDR5 Register (RCD), DDR5 Data Buffer (DB) and DDR5 Thermal Sensor (TS) device for DDR5 RDIMM/LRDIMM family. The presentation will provide the detail tutorial of management bus interface using the I3C basic interface standard for DDR5 DIMM family of products.

3:15-3:30PMBreak
3:30-3:45PM

DDR5 SI and PI Challenges

Presenter: SJ Park, Samsung

More details coming soon.

3:45-4:15PM

Wrap Up

Presenter: Chris Cox, Intel
4:15-5:00PM

Final Q&A

Program, topics and speakers subject to change without notice.