JEDEC DDR5 Workshop: Day 1 Agenda

Wednesday, May 25 • Santa Clara, CA

JEDEC’s DDR5 Workshop will offer an unparalleled opportunity to receive an in-depth technical review of the DDR5 standard as taught by industry experts involved in its development.  The Workshop will include detailed technical content that builds on previous generation devices and assumes that attendees are well-versed in previous generation memory technologies and standards. All attendees who do not already have an in-depth understanding of memory technology and/or memory interface design should also attend the Memory Tutorial session on May 24th in order to maximize their comprehension of the material presented during the two-day DDR5 Workshop.

8:30-9:30AMOnsite check-in for registered attendees

9:30-9:50AM
 

DDR5 Workshop Introduction

Presenter: Christopher Cox, Montage

This presentation will introduce attendees to the speakers and topics that will be covered during the two-day workshop.

9:50-10:00AM

Welcome Remarks

Mian Quddus, JEDEC Chairman

10:00-11:00AM
 

Why DDR5? DDR5

Presenter: Jonathan Hinkle, Lenovo

The DRAM and main memory of computing systems is one of the most critical components to system performance and since the earliest memory devices, JEDEC has set the standards used by all of the industry. The next definition of DRAM has now emerged in its final form with the release of the DDR5 specification, in response to assessments regarding future system requirements, memory architectural considerations and memory device manufacturing considerations. This presentation will review the key system and memory device requirements that drove the definition of the DDR5 industry standard.

11:00AM-Noon
 

 

DDR5 Training Modes

Presenter: Howard David, Synopsys

With data rates increasing significantly for DDR5, the need for training becomes critical. In this presentation, Howard David of Synopsys will walk us through several of the new training modes added to the DDR5 spec as wells as some of those training modes that were enhanced for DDR5 over DDR4.

Noon-1:00PMLunch
1:00-2:30PM
 

DDR5: Accessing the DRAM & Maintaining the Data

Presenter: Matt Prather, Micron

In this presentation, Matt Prather of Micron will walk us through the read and write operations then dive into the new refresh modes such as Same Bank Refresh and Refresh Management.

2:30-3:30PM
 

DDR5 RAS Features and Utilization (On-Die ECC, Transparency, Error Scrub, PPR, Bounded Fault)

Presenter: Keith Kim, SK Hynix

This presentation will cover connectivity, on-die ECC and its value to the industry, error check scrub (manual and automatic modes) and its related transparency modes, and post-package repair (both soft and hard PPR).

3:30-4:30PM
 

 

DDR5 In System Test 

Presenter: Barb Aichinger, FuturePlus

DDR5 is now up and running in the lab. There are two high speed channels, Double Data Rate and Single Data Rate signals. UDIMMs, RDIMMs and SODIMMs modules are all pinned out differently and these modules have PMICs, SPD, HUB, TS’s, and RCD. This presentation will review the lab validation problems facing engineers currently working on DDR5. See how engineers are solving these problems and what challenges they face.

4:30-5:15PM

Round Table Q&A

Program, topics and speakers subject to change without notice.