JEDEC Committee:

DRAM Modules JC-45

The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.

Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.


Status (status)
JC-45.1 Registered DRAM Modules
JC-45.3 Unbuffered DRAM Modules
JC-45.4 Fully Buffered DRAM Modules
JC-45.5 Module Interconnect
JC-45.6 Hybrid Modules

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Membership Information

Committee Meetings

Eindhoven 5 - 9 Jun 2017
Chicago 28 - 1 Sep 2017
San Francisco 4 - 8 Dec 2017
Taipei 5 - 8 Mar 2018
Vancouver 4 - 7 Jun 2018

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