Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-45 DRAM Modules
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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Recent Documents
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex | JESD323-A0-RCC | Dec 2024 |
DDR5 DIMM Labels | JESD401-5C | Nov 2024 |
Compression Attached Memory Module (CAMM2) Common Standard | JESD318A Ver. 1.10 | Nov 2024 |
DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC | JESD323-B4-RCD | Nov 2024 |
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex | JESD323-A0-RCA | Nov 2024 |
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A Annex | JESD324-V0-RCA | Nov 2024 |
LPDDR5/5X Compression Attached Memory Module (CAMM2) Raw Card E Annex | JESD318-F0-RCE | Nov 2024 |
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex | JESD323-A0-RCA | Nov 2024 |
DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card D Annex | JESD324-W4-RCD | Nov 2024 |
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card C Annex | JESD324-V0-RCC | Nov 2024 |