Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-45 DRAM Modules
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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Recent Documents
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®) | JESD325 | Sep 2024 |
DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS | JESD400-5C | Sep 2024 |
JEDEC Module Sideband Bus (SidebandBus) | JESD403-1C.01 | Aug 2024 |
LPDDR5/5X Serial Presence Detect (SPD) Contents | JESD406-5 | Jun 2024 |
JEDEC® Memory Module Label – for Compute Express Link® (CXL®) | JESD405-1B | Jun 2024 |
DDR5 DIMM Labels | JESD401-5B.01 | May 2024 |
JEDEC® Memory Module Reference Base Standard – for Compute Express Link® (CXL®) | JESD317A | Mar 2024 |
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification | JESD323 | Jan 2024 |
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard | JESD308A | Jan 2024 |
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification | JESD324 | Jan 2024 |