Global Standards for the Microelectronics Industry
JC-45 DRAM Modules
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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|DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS||JESD400-5B||Oct 2023|
|DDR5 DIMM Labels||JESD401-5B||Aug 2023|
|Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE4.20.25.K.01||Aug 2023|
|DDR4 NVDIMM-N Design Standard||JESD248A.01||Apr 2023|
|Compute Express Link (CXL™) Memory Module Base Standard||JESD317||Mar 2023|
|Compute Express Link (CXL) Memory Module Label||JESD405-1||Feb 2023|
|Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification||MODULE4.20.26.F||Feb 2023|
|JEDEC MODULE SIDEBAND BUS (SidebandBus)||JESD403-1B||Aug 2022|
|DDR5 SODIMM Raw Card Annex B. Version 1.0||JESD309-S0-RCB||Aug 2022|
|DDR5 UDIMM Raw Card Annex E||JESD308-U4-RCE||Jul 2022|