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Standards & Documents
Search Standards & Documents
Recently Published Documents
Technology Focus Areas
Main Memory: DDR SDRAM
Mobile Memory: LPDDR, Wide I/O
Flash Memory: SSDs, UFS, e.MMC, XFMD
Memory Configurations: JESD21-C
Memory Module Design File Registrations
Wide Bandgap Power Semiconductors: GaN, SiC
Registered Outlines: JEP95
JEP30: Part Model Guidelines
ESD: Electrostatic Discharge
Lead-Free Manufacturing
Type Registration, Data Sheets
Order JEDEC Standard Manufacturer's ID Code
Order ID Code for Low Power Memories
Copyright Information
Document Translation
About JEDEC Standards
Committees
All Committees
JC-11: Mechanical Standardization
JC-13: Government Liaison
JC-14: Quality and Reliability of Solid State Products
JC-15: Thermal Characterization Techniques for Semiconductor Packages
JC-16: Interface Technology
JC-40: Digital Logic
JC-42: Solid State Memories
JC-45: DRAM Modules
JC-63: Multiple Chip Packages
JC-64: Embedded Memory Storage & Removable Memory Cards
JC-70: Wide Bandgap Power Electronic Conversion Semiconductors
News
News
JEDEC Awards: 2024 Honorees
JEDEC Awards: Distinguished Members Recognition
In Memoriam
JEDEC Quality & Reliability Task Group in China
Media Kit
Events & Meetings
All Events & Meetings
Automotive Electronics Forum
JEDEC DDR5 Workshop: Recordings for Sale
Join
Apply for Membership
Membership Benefits
Membership Dues & Details
About
Overview
Member List
Board of Directors
Committee Chairs
Industry Collaboration
Policies & Governance
Patent Policy
JEDEC History
Pre-1960s
1960s
1970s
1980s
1990s
2000s
2010s
Contact
RSS Feeds
JEDEC Staff
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Year in Review: 2023
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Recent Documents
ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS:
JESD12-1B
Aug 1993
CMOS SEMICUSTOM DESIGN GUIDELINES:
JEP116
Nov 1991
ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS:
JESD12-6
Mar 1991
ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES:
JESD12-5
Aug 1988
ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS:
JESD12-4
Apr 1987
ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD:
JESD12-3
Jun 1986
ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET:
JESD12-2
Feb 1986
SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET):
JESD12
Jun 1985