JEDEC Committee:
JC-44

Search by Keyword or Document Number

ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS:	JESD12-1B	Aug 1993
CMOS SEMICUSTOM DESIGN GUIDELINES:	JEP116	Nov 1991
ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS:	JESD12-6	Mar 1991
ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES:	JESD12-5	Aug 1988
ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS:	JESD12-4	Apr 1987
ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD:	JESD12-3	Jun 1986
ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET:	JESD12-2	Feb 1986
SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET):	JESD12	Jun 1985