Global Standards for the Microelectronics Industry
JC-40 Digital Logic
The products within JC-40's scope include digital integrated circuits without regard to their fabrication technology. The committee develops the definition of test parameters and their methods of measurement, and registration formats to promote standardization of type designations.
To accomplish these functions, the committee cooperates with other JEDEC committees and organizations on matters of terms and definitions, mechanical standardization, international standardization, and government liaison. The committee also maintains liaisons with user organizations to promote wide acceptance of the committee’s output.
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|STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:||JESD82-4B.01||Oct 2021|
|DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS||JESD82-14A.01||Oct 2021|
|DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS||JESD82-9B.01||Oct 2021|
|DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS||JESD82-16A.01||Oct 2021|
|DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01)||JESD82-511||Aug 2021|
|PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1||JESD301-1||Jun 2020|
|DDR4 DATA BUFFER DEFINITION (DDR4DB02)||JESD82-32A||Aug 2019|
|DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)||JESD82-31A||Aug 2019|
|DDR4 PROTOCOL CHECKS||JEP175||Jul 2017|
|LRDIMM DDR3 MEMORY BUFFER (MB)||JESD82-30||Oct 2014|