JEDEC Committee:
JC-45 DRAM Modules

The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.

Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.


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Recent Documents

Annex M, Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Document Release 2 SPD4.1.2.M-2 Aug 2018
Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification MODULE4.20.26.F Aug 2018
Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification MODULE4.20.25.D Aug 2018
Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification MODULE4.20.25.K Aug 2018
Annex H, Raw Card H, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification MODULE4.20.28.H Mar 2018
DDR4 NVDIMM-N DESIGN SPECIFICATION JESD248A Mar 2018
Annex G, Raw Card G, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification MODULE4.20.25.G Feb 2018
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification MODULE4.20.26 Feb 2018
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification MODULE4.20.26.E Feb 2018
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification MODULE4.20.28.E Nov 2017

Subcommittees

  • JC-45.1: Registered DRAM Modules
  • JC-45.3: Unbuffered DRAM Modules
  • JC-45.4: Fully Buffered DRAM Modules
  • JC-45.5: Module Interconnect
  • JC-45.6: Hybrid Modules

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Membership Information

Committee Meetings

Maui 3 - 6 Dec 2018
Milan 4 - 7 Mar 2019
Vancouver 3 - 6 Jun 2019
Wailea 2 - 5 Dec 2019
Jeju 2 - 5 Mar 2020