Global Standards for the Microelectronics Industry
JC-45 DRAM Modules
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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|DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard
|JEDEC® Memory Module Label – for Compute Express Link® (CXL®)
|DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification
|DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification
|JEDEC Module Sideband Bus (SidebandBus)
|Compression Attached Memory Module (CAMM2) Common Standard
|JESD318 Ver. 1.02
|DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS
|DDR5 DIMM Labels
|Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification
|DDR4 NVDIMM-N Design Standard