JEDEC Committee:
JC-45 DRAM Modules

The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.

Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.


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Subcommittees

  • JC-45.1: Registered DRAM Modules
  • JC-45.3: Unbuffered DRAM Modules
  • JC-45.4: Fully Buffered DRAM Modules
  • JC-45.5: Module Interconnect
  • JC-45.6: Hybrid Modules

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Membership Information

Committee Meetings

7 - 10 Dec 2020
Shanghai 1 - 4 Mar 2021
Seattle 7 - 10 Jun 2021
Denver 30 Aug - 2 Sep 2021
Waikoloa 6 - 9 Dec 2021