Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-42 Solid State Memories
The products within JC-42's scope include all memory integrated circuits and programmable logic devices, whether static or dynamic, without regard to their fabrication technology or application. Examples include large static and dynamic RAMs, ROMs, EEPROMs, and PLDs. Activities include the development of technical information and standards pertaining to pinouts, operational characteristics including reading and writing algorithms, test parameters, characterization, and registration formats. The committee maintains liaisons with other JEDEC committees and outside organizations to promote wide acceptance of the committee’s actions.
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Recent Documents
NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION | JEP300-1 | Mar 2021 |
SYSTEM LEVEL ROWHAMMER MITIGATION | JEP301-1 | Mar 2021 |
HIGH BANDWIDTH MEMORY (HBM) DRAM | JESD235D | Mar 2021 |
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) | JESD209-4-1A | Feb 2021 |
Addendum No. 1 to JESD79-4, 3D STACKED DRAM | JESD79-4-1B | Feb 2021 |
STANDARD MANUFACTURERS IDENTIFICATION CODE | JEP106BC | Feb 2021 |
GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD | JESD250C | Feb 2021 |
DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD | JESD404-1 | Nov 2020 |
DDR5 SDRAM | JESD79-5 | Jul 2020 |
TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES | JESD402-1 | Jul 2020 |