Global Standards for the Microelectronics Industry
JC-40 Digital Logic
The products within JC-40's scope include digital integrated circuits without regard to their fabrication technology. The committee develops the definition of test parameters and their methods of measurement, and registration formats to promote standardization of type designations.
To accomplish these functions, the committee cooperates with other JEDEC committees and organizations on matters of terms and definitions, mechanical standardization, international standardization, and government liaison. The committee also maintains liaisons with user organizations to promote wide acceptance of the committee’s output.
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|PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1||JESD301-1||Jun 2020|
|DDR4 DATA BUFFER DEFINITION (DDR4DB02)||JESD82-32A||Aug 2019|
|DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)||JESD82-31A||Aug 2019|
|DDR4 PROTOCOL CHECKS||JEP175||Jul 2017|
|LRDIMM DDR3 MEMORY BUFFER (MB)||JESD82-30||Oct 2014|
|DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS||JESD82-29A||Dec 2010|
|FBDIMM: ADVANCED MEMORY BUFFER (AMB)||JESD82-20A||Mar 2009|
|FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)||JESD82-28A||Jul 2008|
|DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS||JESD82-19A||May 2007|
|DEFINITION OF THE SSTUB32869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS:||JESD82-27||May 2007|