Global Standards for the Microelectronics Industry
JC-16 Interface Technology
The activities within JC-16’s scope include the specification of power supply voltage levels for digital integrated circuits and the definition of electrical interfaces between the components of a system. The committee scope further encompasses interface protocols, modeling, simulation, testing environments, and verification.
JC-16 also hosts efforts on operating environment specifications that are common to JC-40, JC-42, and JC-45. The committee maintains a liaison with other JEDEC committees and appropriate outside organizations, both in formulating standards and in promoting wide acceptance of the committee’s activities.
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|PART MODEL SCHEMAS||JEP30-10v3-0-0||Aug 2023|
|Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements||JEP30-E100B||Aug 2023|
|POD15 - 1.5 V PSEUDO OPEN DRAIN I/O||JESD8-20A.01||Aug 2022|
|POD135 - 1.35 V PSEUDO OPEN DRAIN I/O||JESD8-21C.01||Jun 2022|
|POD125 - 1.25 V PSEUDO OPEN DRAIN I/O||JESD8-30A.01||Jun 2022|
|SERIAL INTERFACE FOR DATA CONVERTERS||JESD204C.01||Jan 2022|
|1.05 V CMOS||JESD8-34||Apr 2020|
|0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)||JESD8-33||Jun 2019|
|1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE||JESD8-31||Mar 2018|
|0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)||JESD8-29||Dec 2016|