Global Standards for the Microelectronics Industry
Mobile Memory: LPDDR, Wide I/O
LPDDR5 & LPDDR5X
First published in August 2014 and most recently updated in June 2021, JESD209-4 LPDDR4 is designed to significantly boost memory speed and efficiency for mobile devices. LPDDR4 will eventually operate at an I/O rate of 4266 MT/s, twice that of LPDDR3. To achieve this performance, the committee completely redesigned the architecture, going from a one-channel die with 16 bits per channel to a two-channel die with 16 bits per channel, for a total of 32 bits. Download JESD209-4D.
LPDDR4X JESD209-4-1A, Addendum No. 1 to JESD209-4, Low Power Double Data Rate 4X was updated in February 2021. LPDDR4X is an optional extension intended to offer product designers options for further power reduction as well as on die termination (ODT) flexibility. In LPDDR4X, the I/O supply voltage (VDDQ) is reduced from 1.1 V to 0.6 V. This 40% voltage reduction leads to much lower power usage when sending and receiving data from the memory device, which is particularly beneficial for smartphones and other handheld devices. In addition, LPDDR4X supports easily programmable command bus termination for high memory density systems.
Wide I/O & Wide I/O 2
Published in September 2014, Wide I/O 2 offers a significant speed increase over Wide I/O, while retaining Wide I/O’s vertically stacked through silicon via (TSV) architecture and optimized packaging. Combined, these characteristics position Wide I/O 2 to deliver the ever-increasing speed, capacity, and power efficiency demanded by mobile devices such as smartphones, tablets and handheld gaming consoles. Download JESD229-2.
Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.
Wide I/O 2 mobile DRAM is an extension of the breakthrough technology pioneered with the publication of Wide I/O. Just as switching to multicore processors significantly increased overall computer speed without the need to jump to a new process node, so the vertically stacked architecture allows the Wide I/O 2 interface to deliver four times the bandwidth of LPDDR4 DRAM for around one quarter of the I/O speed.
With the recent publication of LPDDR4, these two new standards from JEDEC offer designers a range of mobile memory solutions, allowing for maximum flexibility. Designers working with a horizontal architecture can choose LPDDR4, while those working with a vertical architecture are supported by Wide I/O 2. In either case, the committee worked to deliver the memory performance that the market requires.
Published in December 2011 by JC-42.6, Wide I/O Mobile DRAM is a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Download JESD229 Wide I/O Single Data Rate (SDR).
Wide I/O Mobile DRAM uses chip-level three dimensional (3D) stacking with Through Silicon Via (TSV) interconnects and memory chips directly stacked upon a System on a Chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GBps, such as 3D Gaming, HD Video (1080p H264 video, pico projection), simultaneously-running applications, etc. Wide I/O will provide the ultimate in performance, energy efficiency and small size for smartphones, tablets, handheld gaming consoles and other high performance mobile devices.
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|Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS||MCP3.12.1||Mar 2023|
|LOW POWER DOUBLE DATA RATE 5 (LPDDR5)||JESD209-5B||Jun 2021|
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4D||Jun 2021|
|JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES||JEP166D||Apr 2021|
|ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)||JESD209-4-1A||Feb 2021|
|LOW POWER DOUBLE DATA RATE (LPDDR5)||JESD209-5A||Jan 2020|
|0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)||JESD8-33||Jun 2019|
|LOW POWER DOUBLE DATA RATE 5 (LPDDR5)||JESD209-5||Feb 2019|
|0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)||JESD8-29||Dec 2016|
|LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)||JESD209-3C||Aug 2015|
Events and Meetings
|JC-16,40,42,45,63,64||Jeju||5 - 8 Jun 2023|
|JC-16,40,42,45,63,64||Vancouver||28 - 31 Aug 2023|
|JC-16,40,42,45,63,64||Maui||4 - 7 Dec 2023|
|JC-16,40,42,45,63,64 Committees||Lisbon||3 - 7 Mar 2024|
|JC-16,40,42,45,63,64 Committees||Denver||3 - 6 Jun 2024|