Mobile Memory: LPDDR

Ever-increasing expectations for mobile device performance are driving the need for versatile mobile memory solutions. Users and suppliers are collaborating to develop the JEDEC standards needed to define those solutions.
 

LPDDR6

JEDEC’s JC-42.6 Subcommittee for Low Power Memories is developing the next generation of its popular LPDDR memory standard: LPDDR6.  To significantly boost memory speed and efficiency for a variety of uses including mobile devices and AI, development plans for LPDDR6 include a focus on:

  • Increasing Bandwidth: To support AI applications and HPC use cases, various highfrequency enablers are being considered
  • Lowering Power Usage: LPDDR6 will continue to reduce power as compared to the prior version of the standard
  • Enhanced RAS (Reliability, Availability and Serviceability) to improve security and performance

As with all JEDEC standards development activities, industry participation is welcome. Learn more about membership and join today.

JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC Board of Directors.

LPDDR5 & LPDDR5X

The latest version of JEDEC LPDDR5 and LPDDR5X, JESD209-5C was published in July 2023. Taken together, LPDDR5 and LPDDR5X are designed to significantly boost memory speed and efficiency for a variety of uses including mobile devices, such as 5G smartphones and artificial intelligence (AI) applications. Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, JESD209-5C is available for download from the JEDEC website.
 

LPDDR4

First published in August 2014 and most recently updated in June 2024, JESD209-4 LPDDR4 is designed to significantly boost memory speed and efficiency for mobile devices. To achieve performance improvements, the committee completely redesigned the architecture, going from a one-channel die with 16 bits per channel to a two-channel die with 16 bits per channel, for a total of 32 bits. Download JESD209-4E.

LPDDR4X JESD209-4-1A, Addendum No. 1 to JESD209-4, Low Power Double Data Rate 4X was updated in February 2021.  LPDDR4X is an optional extension intended to offer product designers options for further power reduction as well as on die termination (ODT) flexibility.  In LPDDR4X, the I/O supply voltage (VDDQ) is reduced from 1.1 V to 0.6 V.  This 40% voltage reduction leads to much lower power usage when sending and receiving data from the memory device, which is particularly beneficial for smartphones and other handheld devices.  In addition, LPDDR4X supports easily programmable command bus termination for high memory density systems.

LPDDR3

LPDDR3 preserves the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management. Download JESD209-3C.
 

LPDDR2

First published in April 2009 and most recently updated in June 2013, the JEDEC LPDDR2 standard (JESD209-2F) offers advanced power management features, a groundbreaking shared interface for nonvolatile memory (NVM) and volatile memory (SDRAM), and a range of densities and speeds. The standard will enhance the design of such products as smart phones, cell phones, PDAs, GPS units, handheld gaming consoles, and other mobile devices by enabling increased memory density, improved performance, smaller size, overall reduction in power consumption as well as a longer battery life.  Download JESD209-2F.

 

Wide I/O & Wide I/O 2

Published in September 2014, Wide I/O 2 offers a significant speed increase over Wide I/O, while retaining Wide I/O’s vertically stacked through silicon via (TSV) architecture and optimized packaging. Combined, these characteristics position Wide I/O 2 to deliver the ever-increasing speed, capacity, and power efficiency demanded by mobile devices such as smartphones, tablets and handheld gaming consoles. Download JESD229-2. 

Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.

Wide I/O 2 mobile DRAM is an extension of the breakthrough technology pioneered with the publication of Wide I/O. Just as switching to multicore processors significantly increased overall computer speed without the need to jump to a new process node, so the vertically stacked architecture allows the Wide I/O 2 interface to deliver four times the bandwidth of LPDDR4 DRAM for around one quarter of the I/O speed.

With the recent publication of LPDDR4, these two new standards from JEDEC offer designers a range of mobile memory solutions, allowing for maximum flexibility. Designers working with a horizontal architecture can choose LPDDR4, while those working with a vertical architecture are supported by Wide I/O 2. In either case, the committee worked to deliver the memory performance that the market requires.

Published in December 2011 by JC-42.6, Wide I/O Mobile DRAM is a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Download JESD229 Wide I/O Single Data Rate (SDR).

Wide I/O Mobile DRAM uses chip-level three dimensional (3D) stacking with Through Silicon Via (TSV) interconnects and memory chips directly stacked upon a System on a Chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GBps, such as 3D Gaming, HD Video (1080p H264 video, pico projection), simultaneously-running applications, etc.  Wide I/O will provide the ultimate in performance, energy efficiency and small size for smartphones, tablets, handheld gaming consoles and other high performance mobile devices. 

Memory MCP

Memory Multiple Chip Package (MCP) stacks multiple chips into a single package, offering increased spatial density and performance benefits, while reducing overall power consumption. This enables designers to pack more functionality into a smaller form factor, facilitating the development of smaller electronic devices.
 
JEDEC Committee JC-63 for Multiple Chip Package is working to enable the MCP market. Manufacturers likely to produce chips to be sold in an MCP form have common ballouts on the chips being defined in JEDEC, thereby facilitating the use of multiple vendors’ devices in one MCP solution. JC-63 also defines MCP packages for mixed technologies.

Search by Keyword or Document Number

Events and Meetings

JC-16,40,42,45,63,64 Hsinchu 2 - 5 Jun 2025
JC-16,40,42,45,63,64 Vancouver 25 - 28 Aug 2025
JC-16,40,42,45,63,64 Waikoloa, The Big Island 1 - 4 Dec 2025
JC-16,40,42,45,63,64 Committees Nashville 2 - 5 Mar 2026
JC-16,40,42,45,63,64 Committees Sapporo 31 May - 4 Jun 2026

See more committee meetings »

Related Committees and Subcommittees

JC-42.6 Low Power Memories
JC-63 Multiple Chip Packages