First published in August 2014 and most recently updated in March 2017, JESD209-4 LPDDR4 is designed to significantly boost memory speed and efficiency for mobile devices. The latest revision of LPDDR4 offers several updates intended to achieve even higher performance over the previous version of the standard, including addition of a single-channel die option for smaller applications; addition of new MCP, PoP and IoT packages; and additional definition and timing improvements for the highest 4266 Mbps speed grade. JESD209-4B LPDDR4 is available for free download with registration.
LPDDR4X is an optional extension intended to offer product designers options for further power reduction as well as on die termination (ODT) flexibility. In LPDDR4X, the I/O supply voltage (VDDQ) is reduced from 1.1 V to 0.6 V. This 40% voltage reduction leads to much lower power usage when sending and receiving data from the memory device. In addition, LPDDR4X supports easily programmable command bus termination for high memory density systems. JESD-209-4-1 is available for free download with registration.
Published in September 2014, Wide I/O 2 offers a significant speed increase over Wide I/O, while retaining Wide I/O’s vertically stacked through silicon via (TSV) architecture and optimized packaging. Combined, these characteristics position Wide I/O 2 to deliver the ever-increasing speed, capacity, and power efficiency demanded by mobile devices such as smartphones, tablets and handheld gaming consoles. Download JESD229-2 free of charge with registration.
Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.
Wide I/O 2 mobile DRAM is an extension of the breakthrough technology pioneered with the publication of Wide I/O. Just as switching to multicore processors significantly increased overall computer speed without the need to jump to a new process node, so the vertically stacked architecture allows the Wide I/O 2 interface to deliver four times the bandwidth of LPDDR4 DRAM for around one quarter of the I/O speed.
With the recent publication of LPDDR4, these two new standards from JEDEC offer designers a range of mobile memory solutions, allowing for maximum flexibility. Designers working with a horizontal architecture can choose LPDDR4, while those working with a vertical architecture are supported by Wide I/O 2. In either case, the committee worked to deliver the memory performance that the market requires.
Published in December 2011 by JC-42.6, Wide I/O Mobile DRAM is a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Download JESD229 Wide I/O Single Data Rate (SDR) free of charge with registration.
Wide I/O Mobile DRAM uses chip-level three dimensional (3D) stacking with Through Silicon Via (TSV) interconnects and memory chips directly stacked upon a System on a Chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GBps, such as 3D Gaming, HD Video (1080p H264 video, pico projection), simultaneously-running applications, etc. Wide I/O will provide the ultimate in performance, energy efficiency and small size for smartphones, tablets, handheld gaming consoles and other high performance mobile devices.
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4B||Mar 2017|
|ADDENDUM NO. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)||JESD209-4-1||Jan 2017|
|0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)||JESD8-29||Dec 2016|
|JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES||JEP166B||Feb 2016|
|Multichip Packages (MCP) and Discrete eMMC, e2MMC, and UFS||MCP3.12.1||Jan 2016|
|LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)||JESD209-3C||Aug 2015|
|WIDE I/O 2 (WideIO2)||JESD229-2||Aug 2014|
|HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT||JESD8-22B||Apr 2014|
|LOW POWER DOUBLE DATA RATE 2 (LPDDR2)||JESD209-2F||Jun 2013|
|Package-on-Package (PoP) and Internal Stacked Module (ISM)||MCP3_12_02||Jan 2012|