Global Standards for the Microelectronics Industry
Main Memory: DDR4 & DDR5 SDRAM
Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
SAVE THE DATES: JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Santa Clara, CA - October 7-10, 2019
Hsinchu, Taiwan - October 14-16, 2019
Interested in attending? Let us know and we'll notify you by email when registration opens.
The JEDEC DDR5 standard is currently in development in JEDEC's JC-42 Committee for Solid State Memories. JEDEC DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.
Contribute to the development of DDR5: Find out more about JEDEC membership and join today!
- Three data width offerings: x4, x8 and x16
- New JEDEC POD12 (1.2V) interface standard for DDR4
- Differential signaling for the clock and strobes
- Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
- Burst length of 8 and burst chop of 4
- Data masking
- DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
- 512 K page size for x4 devices: reduces power (less activation power), and extends the usefulness of x4 devices, which allow for more efficient EDC solutions for high-end systems
- Programmable refresh: Reducing performance penalty of dense DDR4 devices by allowing for refresh intervals ranging from 1x to .0625x the normal refresh interval
- CRC computation/validation across the data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications
- New CA parity for command/address bus: Providing a low-cost method (parity) to verify the integrity of command and address transfers over a link, for all operations
- Per-DRAM Addressability: Can uniquely select and program DRAMs within a memory structure
- DLL off mode supported
Search by Keyword or Document Number
|GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD||JESD250B||Nov 2018|
|DDR4 NVDIMM-N DESIGN SPECIFICATION||JESD248A||Mar 2018|
|DDR4 PROTOCOL CHECKS||JEP175||Jul 2017|
|DDR4 SDRAM STANDARD||JESD79-4B||Jun 2017|
|Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE4.20.25.E||May 2017|
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4B||Mar 2017|
|Addendum No. 1 to JESD79-4, 3D STACKED DRAM||JESD79-4-1||Feb 2017|
|ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)||JESD209-4-1||Jan 2017|
|DDR4 DATA BUFFER DEFINITION (DDR4DB01)||JESD82-32||Nov 2016|
|LRDIMM DDR3 MEMORY BUFFER (MB)||JESD82-30||Oct 2014|