Global Standards for the Microelectronics Industry
Main Memory: DDR4 & DDR5 SDRAM
Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
JEDEC DDR5
JEDEC published its widely-anticipated JESD79-5 DDR5 SDRAM standard in July 2020. The standard addresses demand requirements being driven by intensive cloud and enterprise data center applications, providing developers with twice the performance and much improved power efficiency. JESD79-5 DDR5 is now available for download from the JEDEC website. Read more about the new DDR5 standard here.
JEDEC DDR4
First published in September 2012 and most recently updated in January 2020, the JEDEC DDR4 standard has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. DDR4 (JESD79-4C) is available for download from the JEDEC website.
JC-42 Committee
Looking towards the future, JEDEC's JC-42 Committee for Solid State Memories stands at the forefront of the ongoing effort to produce next generation memory device standards. As with all JEDEC standards development activities, industry participation is welcome. Learn more about membership and join today.
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Recent Documents
| DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-19A.01 | Oct 2021 |
| DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-10A.01 | Oct 2021 |
| DDR5 SDRAM | JESD79-5A | Oct 2021 |
| DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-14A.01 | Oct 2021 |
| DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS | JESD82-16A.01 | Oct 2021 |
| DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS | JESD82-9B.01 | Oct 2021 |
| STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: | JESD82-4B.01 | Oct 2021 |
| JEDEC MODULE SIDEBAND BUS (SidebandBus) | JESD403-1.01 | Jul 2021 |
| LOW POWER DOUBLE DATA RATE 4 (LPDDR4) | JESD209-4D | Jun 2021 |
| NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION | JEP300-1 | Mar 2021 |
Events and Meetings
| JC-16,40,42,45,63,64 | 6 - 9 Dec 2021 | |
| JC-16,40,42,45,63,64 | 7 - 10 Mar 2022 | |
| JC-16,40,42,45,63,64 | Denver | 6 - 9 Jun 2022 |
| JC-16,40,42,45,63,64 | Anaheim | 29 Aug - 1 Sep 2022 |
| JC-16,40,42,45,63,64 | Maui | 12 - 15 Dec 2022 |
