Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
The JEDEC DDR5 standard is currently in development in JEDEC's JC-42 Committee for Solid State Memories. JEDEC DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.
Learn more about DDR5 at JEDEC's Server Forum event in Santa Clara, CA on Monday, June 19, 2017.
Click here for more information and to register.
Interested in contributing to the development of DDR5? Find out more about JEDEC membership and join today!
Due to popular demand, JEDEC has made the presentations from its DDR4 Workshops available online. With audio and slides captured at the February 2013 Workshop, each presentation is available for immediate download upon purchase. Individual sessions are $40 each, or save $60 and purchase all 9 for just $300. To order visit: http://www.jedec.org/ddr4workshop.
The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4B||Mar 2017|
|Addendum No. 1 to JESD79-4, 3D Stacked DRAM||JESD79-4-1||Feb 2017|
|ADDENDUM NO. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)||JESD209-4-1||Jan 2017|
|DDR4 DATA BUFFER DEFINITION (DDR4DB01)||JESD82-32||Nov 2016|
|DDR4 NVDIMM-N DESIGN STANDARD (Revision 1.0)||JESD248||Sep 2016|
|Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE 4.20.25.E||Sep 2015|
|LRDIMM DDR3 MEMORY BUFFER (MB)||JESD82-30||Oct 2014|
|Annex F, R/C F, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE 4.20.25.F||Aug 2014|
|204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification||MODULE 4.20.18||May 2014|
|Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM||MO-269J||Apr 2014|