Standards & Documents Search: 3D-ICs

2 results

Title	Document #	Date
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions	JEP158	Nov 2009
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Committee(s): JC-14.3, JC-14 Download JEP158 Free download. Registration or login required.
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)	JESD229	Dec 2011
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Committee(s): JC-42.6, JC-42 Download JESD229 Free download. Registration or login required.

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