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Standards & Documents Search: Mobile Memory: LPDDR2, LPDDR3, Wide I/O, Memory MCP
8 results
Results
| Title | Document # | Date |
|---|---|---|
| Multichip Packages (MCP) | MCP3_12_01 | Jan 2013 |
Release No. 22B. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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| HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT | JESD8-22A | Oct 2012 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. Committee(s): JC-16 Free download. Registration or login required. |
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| STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS: | JESD82-2 | Jul 2001 |
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required. |
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| Package-on-Package (PoP) and Internal Stacked Module (ISM) | MCP3_12_02 | Jan 2012 |
Release No. 22. Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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| EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES | JESD51-32 | Dec 2010 |
This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described in this standard are also applicable to single chip packages needing more than 36 electrical connections for the test. Committee(s): JC-15 Free download. Registration or login required. |
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| LOW POWER DOUBLE DATA RATE 2 (LPDDR2) | JESD209-2E | Apr 2011 |
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01F. Patent(s): Patent Letters are available to JEDEC paying members only, via the Members Only Area under All members Free download. Registration or login required. |
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| WIDE I/O SINGLE DATA RATE (WIDE I/O SDR) | JESD229 | Dec 2011 |
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Free download. Registration or login required. |
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| LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3) | JESD209-3 | May 2012 |
This document defines the LPDDR3 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. Patent(s): Patent Letters are available to JEDEC paying members only, via the Members Only Area under All members Committee(s): JC-42.6 Free download. Registration or login required. |
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