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Standards & Documents Search: Main Memory: DDR3 & DDR4 SDRAM
Results 1 - 20 of 47
Results
| Title | Document # | Date |
|---|---|---|
| DDR3 SDRAM STANDARD | JESD79-3E | Jul 2010 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patent(s): Patent Letters are available to JEDEC paying members only, via the Members Only Area under All members Committee(s): JC-42.3 Free download. Registration or login required. |
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| SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules | SPD4_01_02_11 | Aug 2011 |
Release No. 21A. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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| DDR3 DIMM Label | PRN09-NM4 | Oct 2009 |
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 2099.01b Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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| STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS | JESD82-21 | Jan 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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| FBDIMM: ADVANCED MEMORY BUFFER (AMB) | JESD82-20A | Mar 2009 |
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patent(s): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF THE SSTUB32869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS: | JESD82-27 | May 2007 |
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required. |
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| LIST OF PREFERRED VALUES FOR USE ON VARIOUS TYPES OF SMALL SIGNAL AND REGULATOR DIODESStatus: Reaffirmed April 1999, April 2002 | JESD482-A | Aug 1984 |
This standard specifies preferred values to be used on signal and regulator diodes. It will facilitate the standardization for nominal values used on small signal regulator diodes previously established in JEDEC Suggested Standard No. 2. Formerly known as EIA-482-A Committee(s): JC-22.4 Free download. Registration or login required. |
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| DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS | JESD82-26 | May 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-23 | May 2007 |
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. Committee(s): JC-40 Free download. Registration or login required. |
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| SILICON RECTIFIER DIODES: | JESD282B.01 | Nov 2002 |
This standard provided definitions, electrical characteristics circuit technology, letter symbols and registration format for diodes and stacks. It also covers rating and characteristics, manufacturing and performance as well as test practices to demonstrate the performance of semiconductor rectifier diodes and rectifier stacks used for the conversion and/or control of electric power. This version contains minor revisions to JESD282-B, April 2000. This document formerly known as EIA-282-A (February 1990), ANSI/EIA-282-A-1989. Committee(s): JC-22.2 Free download. Registration or login required. |
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| DOUBLE DATA RATE (DDR) SDRAM STANDARD | JESD79F | Feb 2008 |
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required. |
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| STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS: | JESD82-2 | Jul 2001 |
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS: | JESD82-3B | Nov 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16857 14-bit SSTL_2 registered buffer for DDR DIMM applications.The purpose is to provide a standard for the SSTV16857 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40.3 Free download. Registration or login required. |
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| STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: | JESD82-4B | May 2003 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-25 | May 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required. |
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| STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION | JESD82-5 | Jul 2002 |
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS: | JESD82-1A | May 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CV857 PLL clock device for registered PC1600, PC2100, PC2700 and PC3200 DIMM applications. The purpose is to provide a standard for a CV857 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS: | JESD82-6A | Nov 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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| DEFINITION OF THE SSTU32864 1.8-V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS: | JESD82-7A | Oct 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32864 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Free download. Registration or login required. |
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| 204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification, Rev 2.0. | MODULE4_20_18 | Dec 2010 |
Release No. 20A. Item 2114.16, 2114.19 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Committees
- JC-45.1: Registered DRAM Modules (5)
- JC-11: Mechanical (Package Outlines) Standardization (3)
- JC-22.2: Rectifiers, Zeners and Signal Diodes (1)
- JC-45.2: Unbuffered DRAM Modules (1)
- JC-22.4: Rectifiers, Zeners and Signal Diodes (1)
- JC-40.3: RDIMM Support Components (4)
- JC-42.3: DRAM Memories (5)
- JC-45.3: Small DRAM Modules (1)
- JC-40.4: FBDIMM Support Components (4)
- JC-40.5: Logic Validation and Verification (1)
- JC-11.14: Microelectronic Assemblies (2)
- JC-40: Digital Logic (27)
- JC-42: Solid State Memories (2)
- JC-45: DRAM Modules (9)
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