Standards & Documents Search: JC-63: Multiple Chip Packages

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Title	Document #	Date
Multichip Packages (MCP)	MCP3_12_01	Jan 2013
Release No. 22B. Item UI3406, 43.02, UI38.24d, UI49.00, 33.03, 51.02, 52.0, 53.0, 38.27, 122.00, 37.07, 37.06, 63.01, 62.00, 33.12, 48.30 Committee(s): JC-64.2, JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
MCP Overview	MCP3_12_00	Jun 2006
Release No. 16 Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Package-on-Package (PoP) and Internal Stacked Module (ISM)	MCP3_12_02	Jan 2012
Release No. 22. Item 48.18, 48.24, 48.26, 38.21b, 48.06a, 38.26, 48.28, 48.29 Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Silicon Pad Sequence (x16/x32 LPDRAM, x16 PSRAM, x16 NAND). Item JC-63-029	MCP3_12_03	Nov 2006
Release No. 16A Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 2 (LPDDR2)	JESD209-2E	Apr 2011
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01F. Patent(s): Patent Letters are available to JEDEC paying members only, via the Members Only Area under All members Committee(s): JC-42.6, JC-63 Free download. Registration or login required.

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