Standards & Documents Search: JC-14: Quality and Reliability of Solid State Products

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Title	Document #	Date
SOLDER BALL PULL	JESD22-B115A	Aug 2010
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. Committee(s): JC-14.1, JC-14 Download JESD22-B115A Free download. Registration or login required.
POWER CYCLING	JESD22-A122	Aug 2007
This Test Method establishes a uniform method for performing component package power cycling stres test. This specification covers power induced temperature cycling of a packaged component, simulating the non-uniform temperature distribution resulting from a device powering on and off in the application. Committee(s): JC-14.1, JC-14 Download JESD22-A122 Free download. Registration or login required.
CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURES	JEP153	Jan 2008
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Committee(s): JC-14.1, JC-14 Download JEP153 Free download. Registration or login required.
GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESS	JEP154	Jan 2008
This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis. Committee(s): JC-14.1, JC-14 Download JEP154 Free download. Registration or login required.
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION:	JEP156	Mar 2009
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ produc families, as well as individual solid state surface-mount products. Committee(s): JC-14.3, JC-14 Download JEP156 Free download. Registration or login required.
CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE	JP002	Mar 2006
This document will provide insight into the theory behind tin whisker formation as it is known today and, based on this knowledge, potential mitigation practices that may delay the onset of, or prevent tin whisker formation. The potential effectiveness of various mitigation practices will also be briefly discussed. References behind each of the theories and mitigation practices are provided. Committee(s): JC-14.1, JC-14 Download JP002 Free download. Registration or login required.
JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SOLID STATE SURFACE-MOUNT DEVICES	J-STD-020D.1	Mar 2008
This document identifies the classification level of nonhermetic solid-state surface mount devices (SMDs) that are sensitive to moisture-induced stress. It is used to determine what classification level should be used for initial reliability qualification. Once identified, the SMDs can be properly packaged, stored and handled to avoid subsequent thermal and mechanical damage during the assembly solder reflow attachment and/or repair operation. This revision now covers components to be processed at higher temperatures for lead-free assembly. A hard cop version is available for $20 each for IPC/JEDEC members and $40 for nonmembers. Committee(s): JC-14.1, JC-14 Download J-STD-020D.1 Free download. Registration or login required.
JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES (Available in German, www.ihs.com)	J-STD-033C	Jan 2012
NOTE - The Moisture Sensitive Caution Label (figure 3-4) has been editorially revised since originally posted 11/04/05, if you downloaded this file prior to 12/14/05 please download this revised version This document provides SMD manufacturers and users with standardized methods for handling, packing, shipping and use of moisture/reflow sensitive SMDs. Now updated to support components that may need to be processed at higher temperatures, such as lead-free processes, these methods help avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. IPC/JEDEC J-STD-033C helps achieve safe and damage-free reflow with the dry packing process and provides a minimum shelf life of 12 months from the seal date when using sealed dry bags. Committee(s): JC-14.1, JC-14 Download J-STD-033C Free download. Registration or login required.
USER GUIDE FOR MICROCIRCUIT FAILURE ANALYSIS:Status: Rescinded November 2004	JEB16	Jul 1970
This guide defines generalized procedures for the failure analysis of monolithic integrated microelectronic circuits. Although the generalized procedural steps may apply to all microelectronic circuits, additional analysis steps unique to thin/thick film hybrid devices are not covered. Committee(s): JC-14 Download JEB16 Free download. Registration or login required.
DISTRIBUTOR REQUIREMENTS FOR HANDLING ELECTROSTATIC -DISCHARGE SENSITIVE (ESDS) DEVICES: SUPERSEDED BY JESD42, March 1994.Status: Superseded	JEP108-B	Apr 1991
Committee(s): JC-14.1, JC-14 Download JEP108-B Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122G	Oct 2011
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.1, JC-14 Download JEP122G Free download. Registration or login required.
PROCESS FAILURE MODE AND EFFECTS ANALYSIS (FMEA):	JEP131A	May 2005
This publication was created in response to the need for a straight forward FMEA procedure. The objective is to provide a guideline for the application of FMEA techniques to improve quality, reliability and/or consistency of electronic components and subassemblies by continually evaluating processes/products against potential failure modes. Committee(s): JC-14.3, JC-14 Download JEP131A Free download. Registration or login required.
CYCLED TEMPERATURE HUMIDITY BIAS LIFE TEST:	JESD22-A100C	Oct 2007
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Committee(s): JC-14.1, JC-14 Download JESD22-A100C Free download. Registration or login required.
STEADY-STATE TEMPERATURE HUMIDITY BIAS LIFE TEST:	JESD22-A101C	Mar 2009
This standard establishes a defined method and conditions for performing a temperature humidity life test with bias applied. The test is used to evaluate the reliability of non-hermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features which pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Committee(s): JC-14.1, JC-14 Download JESD22-A101C Free download. Registration or login required.
HIGH TEMPERATURE STORAGE LIFE	JESD22-A103D	Dec 2010
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to-failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1, JC-14 Download JESD22-A103D Free download. Registration or login required.
TEMPERATURE CYCLING	JESD22-A104D	Mar 2009
This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. Changes in this revision include requirements that the worst-case load temperature must reach the specific extremes rather than just requiring that the chamber ambient temperature reach the extremes. This ensures that the test specimens will reach the specified temperature extremes regardless of chamber loading. Definitions are provided for Load, Monitoring Sensor, Worst-Case Load Temperature, and Working Zone. The transfer time has been tightened from 5 minutes to 1 minute. Five new test conditions have been added as well as a caution on test conditions which exceed the glass transition temperature of plastic package solid devices. Committee(s): JC-14.1, JC-14 Download JESD22-A104D Free download. Registration or login required.
THERMAL SHOCKStatus: Reaffirmed September 2011	JESD22-A106B	Jun 2004
This test is conducted to determine the resistance of a part to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14.1, JC-14 Download JESD22-A106B Free download. Registration or login required.
SALT ATMOSPHERE:	JESD22-A107B	Jan 2004
This salt Atmosphere test is conducted to determine the resistance of solid state devices to corrosion. It is an accelerated test that simulates the effects of severe seacoast atmosphere on all exposed surfaces. The salt atmosphere test is considered destructive. It is intended for lot acceptance, process monitor, and qualification testing Committee(s): JC-14.1, JC-14 Download JESD22-A107B Free download. Registration or login required.
MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.Status: Rescinded May 2000	JESD22-A112-A	Nov 1995
J-STD-020 is now on revision D. Committee(s): JC-14.1, JC-14 Download JESD22-A112-A Free download. Registration or login required.
PRECONDITIONING OF PLASTIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING	JESD22-A113F	Oct 2008
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow). Committee(s): JC-14.1, JC-14 Download JESD22-A113F Free download. Registration or login required.

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