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Standards & Documents Search: JC-40.5: Logic Validation and Verification, Main Memory: DDR3 & DDR4 SDRAM
1 result
Results
| Title | Document # | Date |
|---|---|---|
| FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx) | JESD82-28A | Jul 2008 |
This FBDIMM DFx document covers Design for Test, Design for Manufacturing and Design for Validation (DFx) requirements and implementation guidelines for Fully Buffered DIMM technology. Patent(s): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Free download. Registration or login required. |
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