Standards & Documents Search: JC-25: Transistors

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Title	Document #	Date
POWER MOSFET ELECTRICAL DOSE RATE TEST METHOD:Status: Reaffirmed April 1999	JEP115	Aug 1989
The purpose of this Test Method is to establish electrical criteria for comparing and specifying power MOSFET performance under high dose rate radiation. Committee(s): JC-25 Download JEP115 Free download. Registration or login required.
USER GUIDELINES FOR IR THERMAL IMAGING DETERMINATION OF DIE TEMPERATURE:	JEP138	Sep 1999
The purpose of these user guidelines is to provide background and an example for the use of an infrared (IR) microscope to determine die temperature of electronic devices for calculations such as thermal resistance. Committee(s): JC-25 Download JEP138 Free download. Registration or login required.
GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM:	JEP145	Feb 2003
This publication is intended as a guideline to establish procedures, consideration and common practices that will allow a manufacturer, an application entity, a system designer and other interested parties to define current capability limitations in the leads of components and power systems with semiconductor components. This is a guideline, not a standardized method, it was developed over several years to clarify questions that had been posed to committee members in their respective engineering functions. Committee(s): JC-25 Download JEP145 Free download. Registration or login required.
TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS:Status: Reaffirmed September 1981, April 1999	JEP65	Dec 1967
This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with formats developed for device registration and defining data. Committee(s): JC-25 Download JEP65 Free download. Registration or login required.
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS:Status: Reaffirmed September 1981, April 1999	JEP69-B	Nov 1973
This publication indicates preferred pinouts for FETs in various package designs. Committee(s): JC-25 Download JEP69-B Free download. Registration or login required.
STANDARD LIST OF VALUES TO BE USED IN POWER TRANSISTOR DEVICE REGISTRATION AND MINIMUM DIFFERENCES FOR DISCRETENESS OF REGISTRATIONS - SUPERSEDED BY EIA-419-A, February 1996.Status: Rescinded	JEP74	Jan 1969
Committee(s): JC-25
RECOMMENDED PRACTICE FOR MEASUREMENT OF TRANSISTOR LEAD TEMPERATURE:	JEP84A	Jun 2004
This publication covers recommended methods for measurement of transistor lead temperatures under various load conditions. The techniques described are sufficiently accurate for most applications. Committee(s): JC-25 Download JEP84A Free download. Registration or login required.
LOW FREQUENCY POWER TRANSISTORS:Status: Reaffirmed September 1981, October 2002	JESD10	Jan 1976
This standard consists of a listing of letter symbols, terms, and definitions that are used in power transistors. It also includes information on JEDEC registration procedures, verification tests, and thermal characteristics. Committee(s): JC-25 Download JESD10 Free download. Registration or login required.
POWER MOSFETS:	JESD24	Jul 1985
This standard contains a listing of terms and definitions and letter symbols; a description of established procedures that are followed in the assignment of semiconductor-industry-type designations to power transistors; electrical verification test; thermal characteristics; and a user's guide. Committee(s): JC-25 Download JESD24 Free download. Registration or login required.
ADDENDUM No. 1 to JESD24 - METHOD FOR MEASUREMENT OF POWER DEVICE TURN-OFF SWITCHING LOSS:Status: Reaffirmed April 1999, October 2002	JESD24- 1	Oct 1989
Describes the method of a typical oscilloscope waveform and the basic test circuit employed in the measurement of turn off loss for bipolar, IGBT and MOSFET power semiconductors. This method can be used as a standard for evaluating power semiconductor turn-off switching loss capability and defines standard terminology that should be referenced within the electronic industry. Committee(s): JC-25 Download JESD24- 1 Free download. Registration or login required.
ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD:Status: Reaffirmed October 2002	JESD24- 2	Jan 1991
This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values. Committee(s): JC-25 Download JESD24- 2 Free download. Registration or login required.
ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD):Status: Reaffirmed	JESD24- 3	Nov 1990
The purpose of this test method is to measure the thermal impedance of the MOSFET under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity if the forward voltage drop of the source-drain is used as the junction temperature indicator. This method is particularly suitable to enhancement mode, power MOSFETs having relatively long thermal response times. This test method may be used to measure the thermal response of junction to a heating pulse, to ensure proper die mountdown to its case, or the dc thermal resistance, by the proper choice of the pulse duration and magnitude if the heating pulse. Committee(s): JC-25 Download JESD24- 3 Free download. Registration or login required.
ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD):Status: Reaffirmed October 2002	JESD24- 4	Nov 1990
The purpose of this test method is to measure the thermal impedance of the Bipolar Transistor under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the base-emitter voltage is used as the junction temperature indicator. This test method is used to measure the thermal response of the junction to a heating pulse. Specifically, the test may be used to measure dc thermal resistance, and to ensure proper die mountdown to its case. This is accomplished through the appropriate choice of pulse duration and heating power magnitude. Committee(s): JC-25 Download JESD24- 4 Free download. Registration or login required.
ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD:Status: Reaffirmed october 2002	JESD24- 5	Aug 1990
This method describes a means for testing the ability of a power switching device to withstand avalanche breakdown. Committee(s): JC-25 Download JESD24- 5 Free download. Registration or login required.
ADDENDUM No. 6 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS:Status: Reaffirmed October 2002	JESD24- 6	Oct 1991
This standard describes in detail the method for thermal measurements of Insulated Gate Bipolar Transistors (IGBTs) and is suitable for use both in manufacturing and application of the devices. The method covers both thermal transient and thermal equilibrium measurements for manufacturing process control and device characterization purposes. Properly implemented, JESD24-6 provides a basis for obtaining realistic thermal parametric values that will benefit supplier's internal effectiveness and will be useful to the design and manufacturer of reliable IGBT circuits. Committee(s): JC-25 Download JESD24- 6 Free download. Registration or login required.
ADDENDUM No. 7 to JESD24 - COMMUTATING DIODE SAFE OPERATING AREA TEST PROCEDURE FOR MEASURING dv/dt DURING REVERSE RECOVERY OF POWER TRANSISTORS:Status: Reaffirmed October 2002	JESD24- 7	Aug 1982
Defines methods for verifying the diode recovery stress capability of power transistors. Committee(s): JC-25 Download JESD24- 7 Free download. Registration or login required.
ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING:Status: Reaffirmed October 2002	JESD24- 8	Aug 1992
Determines the repetitive inductive avalanche switching capability of power switching transistors. Committee(s): JC-25 Download JESD24- 8 Free download. Registration or login required.
ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD:Status: Reaffirmed October 2002	JESD24- 9	Aug 1992
Test method to determine how long a device can survive a short circuit condition with a given drive level. Committee(s): JC-25 Download JESD24- 9 Free download. Registration or login required.
ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES:Status: Reaffirmed October 2002	JESD24-10	Aug 1994
Test method to measure the reverse recovery characteristics of the drain source diode of a power MOSFET. Committee(s): JC-25 Download JESD24-10 Free download. Registration or login required.
ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD:Status: Reaffirmed March 2001, October 2002	JESD24-11	Aug 1996
Test method to measure the equivalent resistance of the gate to source of a power MOSFET. Committee(s): JC-25 Download JESD24-11 Free download. Registration or login required.

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