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Standards & Documents Search: JC-16: Interface Technology, Terminated Logic
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| Title | Document # | Date |
|---|---|---|
| STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): | JESD8-15A | Sep 2003 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. Committee(s): JC-16 Free download. Registration or login required. |
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