Standards & Documents Search: JC-14: Quality and Reliability of Solid State Products

Results 1 - 20 of 126

Results

Title	Document #	Date
NATIONAL ELECTRONIC PROCESS CERTIFICATION STANDARD; GOVERNMENT CONTRACTORS: Removed: August 25, 2003	EIA599-A	Jan 1998
Due to notification from the JC-14.4 subcommittee that the material contained in EIA599 has been replaced by the ISO 9000 series, the JEDEC Board of Directors, at its August 2003 meeting, approved to remove this standard from the JEDEC Free Download Area. Committee(s): JC-14.4
QUALITY SYSTEM ASSESSMENT (SUPERSEDES JESD39-A):	EIA670	Jun 1997
This standard is used by the electronic industry for preparation of audit checklists for assessing compliance of quality systems to the requirements of ANSI/ASQC Q9001 (ISO9001), ANSI/ASQC Q9002 (ISO9002), ANSI/ASQC Q9003 (ISO9003), and ANSI/EIA599, National Electronic Process Certification Standard. It also provides a tool for quality system evaluation in accordance with the guidelines of ANSI/ASQC Q9004 (ISO9004) and the Malcolm Baldrige National Quality Award Criteria. Committee(s): JC-14.4 Download EIA670 Free download. Registration or login required.
SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES: Removed 01/21/04	J-STD-002B	Feb 2003
At the request of IPC, J-STD-002B has been temporarily removed from the free download area until such time when it is revised to include lead-free In its place, JEDEC's Test Method B102-D, Solderability, which includes lead-free, is available for free downloading Committee(s): JC-14.1, JC-13 Download J-STD-002B Free download. Registration or login required.
JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SOLID STATE SURFACE-MOUNT DEVICES	J-STD-020D.01	Mar 2008
This document identifies the classification level of nonhermetic solid-state surface mount devices (SMDs) that are sensitive to moisture-induced stress. It is used to determine what classification level should be used for initial reliability qualification. Once identified, the SMDs can be properly packaged, stored and handled to avoid subsequent thermal and mechanical damage during the assembly solder reflow attachment and/or repair operation. This revision now covers components to be processed at higher temperatures for lead-free assembly. A hard cop version is available for $20 each for IPC/JEDEC members and $40 for nonmembers. Committee(s): JC-14.1, JC-14 Download J-STD-020D.01 Free download. Registration or login required.
JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES (Available in German, www.ihs.com)	J-STD-033B.1	Jan 2007
NOTE - The Moisture Sensitive Caution Label (figure 3-4) has been editorially revised since originally posted 11/04/05, if you downloaded this file prior to 12/14/05 please download this revised version This document provides SMD manufacturers and users with standardized methods for handling, packing, shipping and use of moisture/reflow sensitive SMDs. Now updated to support components that may need to be processed at higher temperatures, such as lead-free processes, these methods help avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. IPC/JEDEC J-STD-033B helps achieve safe and damage-free reflow with the dry packing process and provides a minimum shelf life of 12 months from the seal date when using sealed dry bags. Committee(s): JC-14.1, JC-14 Download J-STD-033B.1 Free download. Registration or login required.
JOINT IPC/JEDEC STANDARD FOR ACOUSTIC MICROSCOPY FOR NONHERMETRIC ENCAPSULATED ELECTRONIC COMPONENTS:Status: Under Revision	J-STD-035	May 1999
This test method defines the procedures for performing acoustic microscopy on non-hermetic encapsulated electronic components. This method provides users with an acoustic microscopy process reflow for detecting defects non-destructively in plastic packages while achieving reproducibility. Committee(s): JC-14.1B Download J-STD-035 Free download. Registration or login required.
MARKING AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES	J-STD-609	May 2007
This standard applies to boards/assemblies, to identify the type of Pb-free or Pb-containing solder used. This standard documents a method for identifying board surface finishes and Printed Circuit Board (PCB) resin systems. This standard applies to PCB base materials and for marking the type of conformal coating utilized on Printed Circuit Board Assemblies (PCBAs). Material and their containers previously marked or labeled according to JESD 97 or IPC-1066 need not be remarked unless agreed upon by the supplier and customer. Committee(s): JC-14.4, JC-14 Download J-STD-609 Free download. Registration or login required.
USER GUIDE FOR MICROCIRCUIT FAILURE ANALYSIS:Status: Rescinded November 2004	JEB16	Jul 1970
This guide defines generalized procedures for the failure analysis of monolithic integrated microelectronic circuits. Although the generalized procedural steps may apply to all microelectronic circuits, additional analysis steps unique to thin/thick film hybrid devices are not covered. Committee(s): JC-14 Download JEB16 Free download. Registration or login required.
DISTRIBUTOR REQUIREMENTS FOR HANDLING ELECTROSTATIC -DISCHARGE SENSITIVE (ESDS) DEVICES: SUPERSEDED BY JESD42, March 1994.Status: Superseded	JEP108-B	Apr 1991
Committee(s): JC-14.1, JC-14 Download JEP108-B Free download. Registration or login required.
GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETS:	JEP110	Jul 1988
This publication is intended for power GaAs FET applications requiring high reliability. An accurate measurement of thermal resistance is extremely important to provide the user with knowledge of the FETs operating temperature so that more accurate life estimates can be made. FET failure mechanisms and failure rates have, in general, an exponential dependence on temperature (which is why temperature-accelerated testing is successful). Because of the exponential relationship of failure rate with temperature, the thermal resistance should be referenced to the hottest part of the FET. Committee(s): JC-14.7 Download JEP110 Free download. Registration or login required.
SYMBOL AND LABELS FOR MOISTURE-SENSITIVE DEVICES	JEP113-B	May 1999
Certain PSMC (Plastic Surface-mount Components) are subject to permanent damage due to moisture-induced failures encountered during high-temperature surface-mount processing unless appropriate precautions are observed. The purpose of this publication is to provide a distinctive symbol and labels to be used to identify those devices that require special packing and handling precautions. Committee(s): JC-14.1 Download JEP113-B Free download. Registration or login required.
GUIDELINES FOR USER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERS - SUPERSEDED BY JESD46, August 1997.Status: Rescinded	JEP117	Apr 1994
Committee(s): JC-14.4 Download JEP117 Free download. Registration or login required.
GUIDELINES FOR GaAs MMIC AND FET LIFE TESTING:	JEP118	Jan 1993
These guidelines apply to monolithic microwave GaAs integrated circuits (MMICs) and their individual component building blocks, such as GaAs field effect transistors (FETs), resistors, and capacitors. The purpose of this document is to define a standard approach for evaluating the expected live of GaAs MMICs so that results from different life tests can be compared and so that wording of this document that the MMIC contains at least one FET, but the use of this document has no such limitation. Committee(s): JC-14.7 Download JEP118 Free download. Registration or login required.
A PROCEDURE FOR EXECUTING SWEAT:	JEP119A	Aug 2003
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Download JEP119A Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES:	JEP122E	Mar 2009
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum of the Failure Rates method. Committee(s): JC-14.1, JC-14 Download JEP122E Free download. Registration or login required.
GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999.Status: Rescinded November 1999	JEP124	Dec 1995
Committee(s): JC-14.4 Download JEP124 Free download. Registration or login required.
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING:	JEP128	Nov 1996
This guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested. Committee(s): JC-14.2 Download JEP128 Free download. Registration or login required.
GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING:	JEP130A	Feb 2006
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Committee(s): JC-14.4 Download JEP130A Free download. Registration or login required.
PROCESS FAILURE MODE AND EFFECTS ANALYSIS (FMEA):	JEP131A	May 2005
This publication was created in response to the need for a straight forward FMEA procedure. The objective is to provide a guideline for the application of FMEA techniques to improve quality, reliability and/or consistency of electronic components and subassemblies by continually evaluating processes/products against potential failure modes. Committee(s): JC-14.3, JC-14 Download JEP131A Free download. Registration or login required.
GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS:	JEP134	Sep 1998
The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis. Committee(s): JC-14.6 Download JEP134 Free download. Registration or login required.

Current search

Search by Keyword or Document Number

Guided search

Click a term to refine your current search.

Standards and Documents Assistance

Contact Julie Carlson, 703-907-7559