Standards & Documents Search: JESD (JEDEC Standards)

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Title	Document #	Date
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42.3, JC-42 Free download. Registration or login required.
FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS:	JESD22-C101E	Dec 2009
This new test method describes a uniform method for establishing charged-device model electrostatic discharge withstand thresholds. The charged-device-model simulates charging/discharging events that occur in production equipment and processes. Potential for CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing. One of many examples is a device sliding down a shipping tube hitting a metal surface. Discharges to devices on unterminated circuit assemblies are also well-modeled by the CDM test. CDM ESD events not only reduce assembly yields but can also produce device damage that goes undetected by factory test and later is the cause of a latent failure. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
DICTIONARY OF TERMS FOR SOLID STATE TECHNOLOGY, Fifth Edition:	JESD88D	Dec 2009
This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry Committee(s): JC-10 Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) - LEAD (Pb) CONTENT	JESD213	Mar 2010
This document is intended to be used by Original Component Manufacturers who deliver electronic components and Original Equipment Manufacturers who are the platform system integrators. It is intended to be applied prior to delivery by the OCMs and may be used by OEM system engineers and procuring activities as well as U.S Government Department of Defense system engineers, procuring activities and repair centers. This Standard establishes the instrumentation, techniques, criteria, and methods to be utilized to quantify the amount of Lead (Pb) in Tin-Lead (Sn/Pb) alloys and electroplated finishes containing at least 3 weight percent (wt%) Lead (Pb) using X-Ray Fluorescence (XRF) equipment. Committee(s): JC-13 Free download. Registration or login required.
EMBEDDED MULTIMEDIACARD(e•MMC) e•MMC/CARD PRODUCT STANDARD, HIGH CAPACITY, including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports, Security Enhancement, Background Operation and High Priority Interrupt (MMCA, 4.41)	JESD84-A441	Mar 2010
The purpose of this standard is the definition of the MMC/e•MMC Electrical Interface, its environment and handling. It provides guidelines for systems designers. The standard also defines a tool box (a set of macro functions and algorithms) that contributes to reducing design-in costs. Patent(s): Patent Letters are available to JEDEC paying members only, via the Members Only Area under All members Committee(s): JC-64.1 Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21	Jul 2010
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
SOLDER BALL PULL	JESD22-B115A	Aug 2010
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES	JESD22-B108B	Sep 2010
The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES	JESD217	Sep 2010
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE	JESD22-A102D	Nov 2010
This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test which employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)	JESD22-A110D	Nov 2010
The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. Committee(s): JC-14.1 Free download. Registration or login required.
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)	JESD22-A115C	Nov 2010
JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Qualification of Integrated Circuits). Machine Model as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only human-body model (HBM) and charged-device model (CDM) are the necessary ESD qualification test methods as specified in JESD47. Committee(s): JC-14.1 Free download. Registration or login required.
TEMPERATURE, BIAS, AND OPERATING LIFE	JESD22-A108D	Nov 2010
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Committee(s): JC-14.1 Free download. Registration or login required.
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES:	JESD22-A111A	Nov 2010
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
TRANSIENT DUAL INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW THROUGH A SINGLE PATH	JESD51-14	Nov 2010
This document specifies a test method (referred to herein as “Transient Dual Interface Measurement”) to determine the conductive thermal resistance “Junction-to-Case” RθJC (θJC) of semiconductor devices with a heat flow through a single path, i.e. semiconductor devices with a high conductive heat flow path from the die surface that is heated to a package case surface that can be cooled by contacting it to an external heat sink. TDIM Master Software: http://www.jedec.org/download/search/TDIM-Master-2011-04-06.zip Committee(s): JC-15 Free download. Registration or login required.
HIGH TEMPERATURE STORAGE LIFE	JESD22-A103D	Dec 2010
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to-failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS	JESD82-29A	Dec 2010
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40.3, JC-40.4, JC-40 Free download. Registration or login required.
EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES	JESD51-32	Dec 2010
This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described in this standard are also applicable to single chip packages needing more than 36 electrical connections for the test. Committee(s): JC-15 Free download. Registration or login required.
SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD	JESD218A	Feb 2011
This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser. Revision A includes further information on SSD Capacity. Committee(s): JC-64.8 Free download. Registration or login required.

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