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Standards & Documents Search: JESD (JEDEC Standards)
Results 1 - 20 of 302
Results
| Title |
Document # |
Date |
|---|---|---|
| LEADLESS CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARS: | JESD1 | Apr 1982 |
This standard shows how to convert existing DIP pinouts for op-amps, comparators, and D/A converters, to chip carrier packages. Committee(s): JC-41 Free download. Registration or login required. |
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| LOW FREQUENCY POWER TRANSISTORS:Status: Reaffirmed September 1981, October 2002 | JESD10 | Jan 1976 |
This standard consists of a listing of letter symbols, terms, and definitions that are used in power transistors. It also includes information on JEDEC registration procedures, verification tests, and thermal characteristics. Committee(s): JC-25 Free download. Registration or login required. |
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| TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS: | JESD100B.01 | Dec 2002 |
A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors, microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and their definitions in this standard have been updated and are in general agreement with the latest publications of the IEEE and the IEC. The companion standard for other integrated circuits is JESD99A. Also included is a system for generating symbols for time intervals found in complex sequential circuits, including memories. JESD100B.01 is the first minor revision of JESD100-B, December 1999. Annex A briefly shows entries that have changed. Committee(s): JC-10 Free download. Registration or login required. |
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| CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS: | JESD11 | Dec 1984 |
This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages. Committee(s): JC-40.2 Free download. Registration or login required. |
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| SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET): | JESD12 | Jun 1985 |
The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of gate array vendors' ability to implement a desired complex function on a particular gate array at a known level of performance. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS: | JESD12-1B | Aug 1993 |
The purpose of this standard is to promote the uniform use of abbreviations, terms, and definitions throughout the semiconductor industry. It is a useful guide for users, manufactures, educators, technical writers, and others interested in the characterization, nomenclature, and classification of semicustom integrated circuits. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET: | JESD12-2 | Feb 1986 |
The purpose of these benchmarks is to provide a common set of high level functions that serve as vehicles for comparing the performance of cell-based ICs implemented in any technology using any internal structure. JESD12-2 extends the gate array benchmark set (JESD12) to cell-based ICs. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD: | JESD12-3 | Jun 1986 |
This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell types are addressed, all of which are commonly used by gate array designers to implement Application Specific Integrated Circuits. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS: | JESD12-4 | Apr 1987 |
This standard defines how to specify various performance parameters of semicustom ICs, including cell and interconnect propagation delays, input/output levels and capacitance, and power dissipation. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES: | JESD12-5 | Aug 1988 |
This standard is intended to provide circuit designers with the information needed to develop complex integrated circuits that can be reliably and economically tested without compromising flexibility. Committee(s): JC-44 Free download. Registration or login required. |
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| ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS: | JESD12-6 | Mar 1991 |
This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the external environment. JESD12-6 is intended to provide the ASIC manufacturer and user with a common set of signal interface levels. The standard defines interface levels for 5 volt operation. Committee(s): JC-44 Free download. Registration or login required. |
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| STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES: | JESD13-B | May 1980 |
This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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| SEMICONDUCTOR POWER CONTROL MODULES:Status: Reaffirmed June 1992, April 1999, April 2002 | JESD14 | Nov 1986 |
Semiconductor Power Control Modules (SPCM) are modules consisting of thyristors or transistors, or both, as the primary controlling elements. Methods of manufacture of semiconductor power control modules include the assembling of individual components and the use of semiconductor hybrids or monolithic processing technologies, or both. Committee(s): JC-22.2 Free download. Registration or login required. |
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| THERMAL MODELING OVERVIEW | JESD15 | Oct 2008 |
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Free download. Registration or login required. |
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| COMPACT THERMAL MODEL OVERVIEW | JESD15-1 | Oct 2008 |
This document should be used in conjunction with the master document, JESD15, and JESD15-2, and subsidiary documents as they become available. This document is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. At present, there are two such documents; JESD15-3, and JESD15-4. Free download. Registration or login required. |
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| TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE | JESD15-3 | Jul 2008 |
This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from the JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this document is limited to single-die packages that can be effectively represented by a single junction temperature. Committee(s): JC-15 Free download. Registration or login required. |
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| DELPHI COMPACT THERMAL MODEL GUIDELINE | JESD15-4 | Oct 2008 |
This guideline specifies the definition and lists acceptable approaches for constructing a compact thermal model (CTM) based on the DELPHI methodology. The purpose of this document is twofold. First, it aims to provide clear guidance to those seeking to create DELPHI compact models of packages. Second, it aims to provide users with an understanding of the methodology by which they are created and validated, and the issues associated with their use. Committee(s): JC-15 Free download. Registration or login required. |
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| ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM):Status: Reaffirmed September 2008 | JESD16-A | Apr 1995 |
This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation. Derivation of any new methods for combing groups for AOQ estimation. Derivation of any new methods introduced into this document have been provided in annexes. A statistical method is based on confidence interval statistics. A procedure was established for reporting AOQ when the minimum sample size criterion is not met. Not all sections of EIA-554 are appropriate for use by device manufacturers therefore JEDEC wishes to continue using JESD16A. In December 2008 the formulating committee approved to remove EIA-554 (July 1996, Reaffirmed September 2002) from the JEDEC website. To obtain a copy of EIA-554 please contact GEIA at http://www.geia.org/ Committee(s): JC-13 Free download. Registration or login required. |
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| LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999Status: Rescinded February 1999 | JESD17 | Aug 1988 |
Committee(s): JC-40.2 Free download. Registration or login required. |
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| STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC: | JESD18-A | Jan 1993 |
The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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