Standards & Documents Search: ddr4

Title	Document #	Date
STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION	JESD82-8.01	Feb 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16. Committee(s): JC-40 Free download. Registration or login required.
Graphics Double Data (GDDR4) SGRAM Standard	SDRAM3_11_05_08	May 2006
Release No. 16. Item 1600.41, 1656.0 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A	Oct 2009
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
DDR4 SDRAM STANDARD	JESD79-4	Sep 2012
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee(s): JC-42.3 Free download. Registration or login required.
Registration - 284 Pin DDR4 DIMM, 0.85 mm Pitch. DIM Item No. 11.14-144	MO-309A	Aug 2012
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 256 Pin, DDR4 SODIMM and GDDR5M Outline, 0.50mm Pitch. DIM Item No. 11.14-146, includes Editorial correction	MO-310A.01	Sep 2012
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 DIMM SMT, 284 Pin Socket Outline, 0.85 mm Pitch. SKT Item No. 14-143	SO-017A	Sep 2012
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 DIMM PTH 284 Pin Socket Outline, 0.85 mm Pitch. SKT Item No. 14-142(E)	SO-016A.01	Oct 2012
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 and GDDR5M Small Outline Dual Inline Memory Module (SODIMM), 256 pin, 0.50mm pitch Socket Outline Item No. 14-145	SO-018A	Oct 2012
Patent(s): Foxconn: 5,882,211; 6,126,472; 6,113,398 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
REGISTRATION - DDR4 DIMM Press Fit 284 Pin Socket Outline, 0.85 mm Pitch. SKT Item 14-147	SO-019A	Dec 2012
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 This is a minor editorial revision, the differences between revisions can be found on page 17 of the document.	JESD79-3-1A.01	May 2013
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. Committee(s): JC-42.3, JC-42 Free download. Registration or login required.
SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules	SPD4_01_02_11	Aug 2012
Release No. 22. Item 2065.45 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 2 to JESD79-3 - 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600	JESD79-3-2	Oct 2011
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required.
LIST OF PREFERRED VALUES FOR USE ON VARIOUS TYPES OF SMALL SIGNAL AND REGULATOR DIODESStatus: Reaffirmed April 1999, April 2002	JESD482-A	Aug 1984
This standard specifies preferred values to be used on signal and regulator diodes. It will facilitate the standardization for nominal values used on small signal regulator diodes previously established in JEDEC Suggested Standard No. 2. Formerly known as EIA-482-A Committee(s): JC-22.4 Free download. Registration or login required.
DOUBLE DATA RATE (DDR) SDRAM STANDARD	JESD79F	Feb 2008
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required.
204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification	MODULE4_20_18	Jan 2013
Release No. 22A. Item 2114.16, 2114.19, 2227.11 Committee(s): JC-45.3, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification	MODULE4_20_19	Jan 2013
Release No. 22A. Item 2131.03, 2078.04, 2131.06 Committee(s): JC-45.2, JC-45.3, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.	MO-269H	Dec 2012
Item 11.14-134 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
R/C M, in 240-Pin, 72 bit-wide, PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification Release No. 22 Item 2145.39	MODULE4_20_23_AnnexM	Jan 2013
Committee(s): JC-45.1, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Lead Centers. DIM	MO-268D	Aug 2012
Item 11.14-135, 11.14-139 Patent(s): Hatachi: 5,227,664 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.

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