|SOLDERABILITY - SUPERSEDED BY J-STD-002D, JUNE 2013Status: Superseded||JESD22-B102E||Oct 2007|
This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment.
|SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES: Removed 01/21/04||J-STD-002B||Feb 2003|
At the request of IPC, J-STD-002B has been removed from the free download area. In its place, JEDEC's Test Method, JESD22-B102, Solderability, which includes lead-free, is available for free downloading.
Any revision to J-STD-002 will no longer be available for free to the industry on the JEDEC website. However, the document is available to the JEDEC formulating Committee members, in the Members Area.
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Contact Julie Carlson, 703-624-9230