Dictionary: JESD88

JEDEC publishes a Dictionary of Terms for Solid State Technology, JESD88. Its purpose is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry. The terms and definitions from JESD88 are provided here for quick search. This area will be updated as new terms and definitions are developed by JEDEC Committees and approved by the JEDEC Board of Directors.

The attachment between a bonding wire and a chip bonding pad or package terminal.

JESD99B, 5/07

A separation of the entire wire bond from the bonding surface with only an imprint being left on the bonding surface. There is very little evidence of intermetallic formation or welding or of disturbance of the bonding surface metallization.

JESD22-B116, 7/98

A separation of the wire bond where 1) a thin layer of the bonding surface metallization remains with the wire bond and an impression is left in the bonding surface, 2) intermetallics remain on the bonding surface and with the wire bond, or 3) a major portion of the wire bond remains on the bonding surface.

JESD22-B116, 7/98

A condition under the die pad metallization in which the insulating layer (oxide or interlayer dielectric) and the bulk material (silicon) separate or chip out. Separation interfaces that show pits or depressions in the insulating layer (not extending into the bulk) are not considered craters. It should be noted that cratering can be caused by several factors including the wire bonding operation, the post-bonding processing, and even the act of shear testing itself. Cratering present prior to the shear test operation is unacceptable.

JESD22-B116, 7/98

A condition produced when the shear tool contacts the bonding surface. This condition may be due to improper placement of the specimen, a low shear height, or instrument malfunction. This bond shear type is not acceptable; the shear value is invalid and shall be eliminated from the shear data.

JESD22-B116, 7/98

A condition produced when the shear tool removes only the topmost portion of the ball or wedge bond. This condition may be due to improper placement of the specimen, a high shear height, or instrument malfunction. This bond shear type is not acceptable; the shear value is invalid and shall be eliminated from the shear data.

JESD22-B116, 7/98

A separation between the bonding surface metallization and the underlying substrate or base material. There is evidence of bonding surface metallization remaining attached to the ball or wedge bond.

JESD22-B116, 7/98

Either the die-pad metallization or the package surface metallization to which the wire is ball-, wedge-, or stitch-bonded.

JESD22-B116, 7/98

A wire that is bonded to a chip bonding pad in order to connect the chip to any other point within the device package.

JESD99B, 5/07

A design methodology in which the I/O buffers of a circuit or functional block are observed and controlled by scan cells.

NOTE The Boundary Scan standard was developed by the Joint Test Action Group (JTAG) and is embodied in IEEE Standard 1149‑1.

JESD12-1B, 8/93
JESD99B, 5/07

The phenomenon, occurring in a reverse-biased semiconductor junction, whose initiation is observed as a transition from a region of high small-signal resistance to a region of substantially lower small-signal resistance for an increasing magnitude of reverse current.

JESD10, 9/81
JESD24, 7/85
JESD77-B, 2/00
JESD282-B, 4/00

A current in a breakdown region.

JESD77-B, 2/00
JESD282-B, 4/00

The portion of the characteristic that starts with the transition from the high dynamic resistance off state to a substantially lower dynamic resistance and extending to the switching point.

JESD77-B, 2/00

The portion of the voltage-current characteristic beyond the initiation of breakdown for an increasing magnitude of reverse current.

JESD77C, 10/09
JESD210, 12/07

A voltage in a breakdown region.

JESD10#, 9/81
JESD24#, 7/85
JESD77-B, 2/00
JESD282-B#, 4/00

The breakdown voltage between the collector and base terminals when the collector terminal is biased in the reverse direction with respect to the base terminal and the emitter terminal is open-circuited.

JESD10, 9/81
JESD77-B, 2/00

The breakdown voltage between the collector and emitter terminals when the collector terminal is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

  • open-circuited.
  • short-circuited to the emitter terminal.

  • returned to the emitter terminal through a specified circuit.

  • returned to the emitter terminal through a specified resistance.

  • returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

JESD10, 9/81

JESD77-B, 2/00

The breakdown voltage between the collector and emitter terminals when the collector terminal is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

  • open-circuited.
  • short-circuited to the emitter terminal.

  • returned to the emitter terminal through a specified circuit.

  • returned to the emitter terminal through a specified resistance.

  • returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

JESD10, 9/81

JESD77-B, 2/00

The breakdown voltage between the collector and emitter terminals when the collector terminal is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

  • open-circuited.
  • short-circuited to the emitter terminal.

  • returned to the emitter terminal through a specified circuit.

  • returned to the emitter terminal through a specified resistance.

  • returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

JESD10, 9/81

JESD77-B, 2/00

The breakdown voltage between the collector and emitter terminals when the collector terminal is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

  • open-circuited.
  • short-circuited to the emitter terminal.

  • returned to the emitter terminal through a specified circuit.

  • returned to the emitter terminal through a specified resistance.

  • returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

JESD10, 9/81

JESD77-B, 2/00

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