settling time to steady-state ramp (of a multiplying digital-to-analog converter) (ts(ramp))

The time interval between the instant a ramp in the reference voltage starts and the instant when the analog output value enters for the last time a specified error band about the final ramp in the output.


JESD99B, 5/07

User login

Enter the password that accompanies your username.
Please note: passwords are now case-sensitive.

Browse Alphabetically

A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

Standards and Documents Assistance

Contact Julie Carlson, 703-624-9230

Dictionary RSS Feed

Subscribe to the JEDEC Dictionary RSS Feed to receive updates when new dictionary entries are added.