- Home
- About JEDEC
- Standards & Documents
- Committees
- JC-10: Terms, Definitions, and Symbols
- JC-11: Mechanical (Package Outlines) Standardization
- JC-13: Government Liaison
- JC-14: Quality and Reliability of Solid State Products
- JC-15: Thermal Characterization Techniques for Semiconductor Packages
- JC-16: Interface Technology
- JC-22: Diodes and Thyristors
- JC-25: Transistors
- JC-40: Digital Logic
- JC-42: Solid State Memories
- JC-45: DRAM Modules
- JC-63: Multiple Chip Packages
- JC-64: Embedded Memory Storage and Removable Memory Cards
- JC-65: RFID
- News
- Events & Meetings
- Join JEDEC
- Members Area
- Order JEP 95 and JESD21-C Related Products
- Privacy Policy
front end of line (FEOL) (noun)
The portion of the semiconductor processing line that creates active devices and ends with the gate-oxide conductors.
References
JEP156, 3/09
Browse Alphabetically
Standards and Documents Assistance
Contact Julie Carlson, 703-624-9230
Dictionary RSS Feed
Subscribe to the JEDEC Dictionary RSS Feed to receive updates when new dictionary entries are added.