A write cycle in which the contents of an entire row of the memory array can be selectively set to the stated value. The "mask" value determines which bit planes are to be altered while the "color register" contains the data value to be written. The color register is loaded in a previous load-color-register cycle with a persistent value. The mask value is supplied during the cycle on the DQ(n) terminals. A new mask value must be supplied for each cycle performed. A high mask bit normally enables the write function for that bit. A low mask bit leaves the data unaltered.
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